Expert Verilog Verification
Advanced Level - 2 daysview dates and locations
Expert Verilog Verification (2 days) is an intensive advanced application course. It teaches engineers how to increase productivity by enhancing their Verilog coding and application skills. The syllabus focuses on test benches and more recent techniques for verification such as scoreboarding and Transaction Level Verification (TLV). Also included is an overview of the SystemVerilog extensions to Verilog, with an assessment of their impact on both design and verification.
Carefully designed workshops comprise 50% of teaching time, and enable engineers to apply their new skills in the context of the latest Verilog design tools, practices and methodologies.
Expert Verilog Verification forms the last 2 days of the 4-day Doulos Expert Verilog course.
Who should attend?Design engineers and verification engineers involved in Verilog test bench development or behavioural modelling for the purpose of functional verification
What will you learn?
- A deeper understanding of the Verilog language and how to apply it, enabling you to troubleshoot Verilog simulation problems more easily
- How recent revisions of the Verilog language and the SystemVerilog extensions will impact and enhance your design and verification activity
- How best to tackle the problem of design verification using Verilog – the principles and practice
- Advanced testbenching - how to structure and write large and complex Verilog test benches
- Techniques for writing behavioural models of hardware components in Verilog
- How to incorporate PLI applications into your Verilog simulations
Pre-requisitesThis is an advanced language and methodology training course. Prior attendance of the Doulos Comprehensive Verilog course (or equivalent) is required, and at least 6 months of ‘live’ project experience using Verilog is strongly recommended.
Course materialsDoulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
- Fully indexed course notes creating a complete reference manual
- Workbook full of practical examples to help you apply your knowledge
- Doulos Verilog Golden Reference Guide for language, syntax, semantics and tips
- Tour guides (to support the tools and technologies of your choice)
Structure and Content
Verification StrategiesVerification flow • Black and white box testing styles • Code analysis to guide testing • Techniques for stimulus generation and output checking
Advanced Verilog for VerificationFine-grain concurrency with fork/join • The Verilog simulation cycle and its impact on coding style • Non-determinism and race hazards • Understanding the effect of delayed signal assignments
Improving the Quality of your Test Fixture CodeStructuring test fixtures with tasks and functions • Tactics for packaging code for maintainability and re-use • Advanced stimulus generators: serial data, complex timing • Software encapsulation: modules, local variables, multiple hierarchies
Transaction-Based Test FixturesBus functional models • Techniques for layering your test fixtures • Using Verilog modules like OO classes • Transaction generation using bus functional models • Re-use and flexibility of test fixture code
MonitoringSpecify blocks • Built-in timing checks • Strobing inputs and sampling outputs • Measuring delays • Storing inputs/outputs in a buffer • Collecting and filtering diagnostic data • Simple data visualisation techniques
Component Modelling IntroductionUses of component modelling • Component modelling methods • Choosing a component model • Structure of a component model • Handling asynchronous inputs • Storing inputs/outputs and sampling outputs • Measuring delays
Modelling and Analysis TechniquesModelling memories • Imitating dynamic allocation in Verilog • Using public domain PLI applications to model large memories • Modelling external analogue subsystems • Signature analysis and other techniques for regression testing • Varying the timing of stimulus • Modelling communcations channels • Random and directed-random tests
Using PLI Libraries (note: no prior experience of C is assumed)Incorporating PLI applications into your simulations • What the PLI can and can’t do • Two generations of the PLI – which to use? • Types of PLI application: functions, stimulus generators, file access, component models • Pointers to functions in C • Function pointer tables • PLI application integration in various simulators
Verilog-2001, Verilog-2005 and SystemVerilog for VerificationA tutorial review of recent changes in the Verilog language that are relevant to verification • Preview of SystemVerilog verification extensions
Optional modules - (Expert Verification)To meet varying specialist interests for team-based training, one or more of these optional modules can be integrated with the course by prior agreement with Doulos. These options are not available on scheduled public courses.
Modelling Analogue HardwareVerilog drive strengths • Modelling I/O primitives such as open-drain and pullup • Verilog switch primitives • Simulating the external analogue world using real numbers and sampled-time
Verilog File I/OReview of Verilog-1995 file I/O mechanisms • Verilog-2001 file I/O model and file reading functions • Reading structured data from text files • File-driven test fixtures
Writing PLI ApplicationsThe PLI option requires a working knowledge of the C programming language.
PLI jargon • VPI and TF/ACC routines • Creating a simple PLI application • Linking PLI code to your Verilog simulation • Callback functions • Stimulus generators • Making PLI applications sensitive to input changes • Writing component models in the PLI
Looking for team-based training, or other locations?
Complete an on-line form and a Doulos representative will get back to you »
Price on request
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