Signal Integrity with Hands-On Simulation
Standard Level - 3 daysview dates and locations
Signal Integrity with Hands-On Simulation is a 3-day training course in practical signal integrity for board level design and layout engineers. The course alternates between teaching the essential theory and how to use simulations as part of day-to-day design work in an efficient way using industry standard IBIS simulators etc. Lots of practical examples and tips are given.
The course gives engineers confidence to handle signal and power integrity while designing board-level digital circuits. The emphasis is on understanding how the theory works for common real-world circuits with multiple digital parts on multilayer PCBs. Delegates learn to use simulations to find the requirements for layout that will work reliably and how to apply that in the design process.
The course is not focused on how to use a specific vendorís toolset but rather how to get useful results using the tools available. The lab exercises are carefully designed to reinforce the theory and put it in a ready-to-use practical form without spending too much time on the specifics of the chosen tool.
Lab exercises comprise approximately 50% of class time.
Who should attend
- Engineers who wish to understand fundamental signal integrity and power integrity on a theoretical and practical level.
- Engineers who want to efficiently apply signal integrity simulation in their design work.
- Engineers who have experience in digital design and/or layout.
Pre-requisitesDelegates must have a good working knowledge of digital hardware design. No previous knowledge of signal integrity or simulation tools is required. No advanced math is required.
What you will learn
- Signal integrity theory and power integrity theory
- Practical solutions to signal integrity imposed requirements
- How to efficiently use simulation tools to estimate and calculate layout requirements
- How to define routing rules for layout based on these requirements
- As an overall result to reduce the number of board spins and improve reliability
Course materialsThe course fees include:
- Full binder of all course material and lab exercises
- Free download of optional supplemental text book by Lee Ritchey: "First Time Right, Volume I" (recommended for further reading)
Structure and Content
IntroductionWhy signal integrity matters • Noise margin and noise sources • Reasons for board spins
Transmission LinesIdeal transmission lines • Lossy transmission lines • Terminology • Calculating impedance • Dialectric constant of prepreg and laminates • Measuring impedance • Why 50 ohms?
ReflectionsFormulas • Recognizing low vs high source impedance • What is reflection and what is ringing?
Termination TechniquesUnterminated transmission lines • Parallel, series and RC termination • Why terminate? • When to terminate • Power consumption of termination
Net TopologiesMulti-node nets •: Where to terminate • One vs. multiple drivers • One vs. multiple loads • Handling of connectors
IBIS SimulationUnderstanding the models • Process corner simulation • When IBIS simulation is not possible
StubsTermination stubs • Understanding the quarter wavelength stub
Bus StructuresPCI bus • SSTL termination • DDR1, DDR2, DDR3, DDR4 schemes • LVDS bus • Typical address and data bus simulation
CrosstalkNear-end vs. far-end crosstalk • Capacitive vs. inductive coupling • Critical length • Reducing crosstalk • Broadside vs. side-by-side • Guard traces • Reference plane
Differential SignallingPrinciple for differential signalling • Advantages and disadvantages • Cable vs. on the board • Immune to common mode coupling? • Does differential routing make sense?
Power Sub-SystemPower distribution model • Voltage ripple requirements • Noise margin considerations
Bypass CapsCapacitor types • Ceramics • RLC models • Multi-terminal capacitors • Bulk capacitors • Land patterns • Effective inductance • Placement around vs. on the back side of a board • Interplane capacitance • Myths about bypass
Designing a Power Distribution Network (PDN)Concept for finding the right amount of bypass • Spreadsheet simulation • PDN tool • Frequency range • Package model • On-package and on-die capacitance • Via inductance • Defining plane requirements
Testing the PDNTest methods • Required equipment • Understanding the test setup and results • Preparing for doing the tests in your lab
Vcc & Ground BounceDefining vcc bounce, ground bounce and SSN • Measuring ground bounce • Package lead inductance • Simple paper estimation • Finding peak I/O current • Simulating SSN with an IBIS simulator
Noise Margin BudgetUnderstanding noise sources on the board • Reflections • Crosstalk • SSN • Power supply variations • Ground offsets • Trace voltage drops and losses • Terminator noise • Skin effect • Dialectric loss • PCI Express example • Vtt example
Creating Routing RulesDesign flow • Building a design rule set • Efficient pre and post layout review technique
Differential signallingSkew and jitter • Loss impact on multi gigabit differential signalling • Pre/de-emphasis and receiver equalization
PCB MaterialsUnderstanding PCB materials • Copper • Prepreg and laminates • Selecting surface finish
PCB Stack-UpDefining the PCB stack-up • Building a design rule set • Efficient pre and post layout review technique
PCB Test FeaturesSpecifying the PCB stack-up • Materials • Patents • Test features for layer order • Test traces • Test points and probes for high-speed
Vias and ModelsVia types • Non-functional pads • Capacitance and inductance • Is the via a stub? • Via models • Understanding CAF • Backdrilling
|May 13th, 2019||Ringwood, UK||Enquire|
|May 21st, 2019||San Jose, CA||Enquire|
|May 27th, 2019||Munich, DE||Enquire|
|September 11th, 2019||Ringwood, UK||Enquire|
|November 4th, 2019||Ankara, TR||Enquire|
|December 9th, 2019||Munich, DE||Enquire|
|indicates CONFIRMED TO RUN courses.|
Looking for team-based training, or other locations?
Complete an on-line form and a Doulos representative will get back to you »
Price on request
Back to top