VMM Adopter Class
Advanced Level - 2 daysview dates and locations
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The Verification Methodology Manual for SystemVerilog (VMM) specifies a functional verification methodology, and defines the VMM Standard Library implemented in SystemVerilog. VMM includes constrained random stimulus generation, functional coverage collection, assertions, and transaction-level modelling. VMM's layered structure and channel-based communication model make it suitable for building both very simple and very complex functional verification environments.
Delegates for this course must start with a working knowledge of SystemVerilog, including its object-oriented programming (class-based) features. This course takes delegates through to full VMM verification project readiness by focussing on the verification principles and the in-depth practical application of the VMM using Synopsys VCS™.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. In the hands-on workshops, delegates will progressively build a complete VMM verification environment for a small example system.
Who should attend?
- Verification engineers who need to develop, deploy or configure SystemVerilog verification environments based on the VMM
- Design engineers who wish to make use of SystemVerilog's verification capabilities and benefit from a standard verification methodology
What will you learn?
- The principles of effective functional verification using SystemVerilog
- How to understand the VMM Standard Library classes, documentation and examples
- How to build complete, powerful, reusable VMM-compliant verification environments
Pre-requisitesA sound working knowledge of SystemVerilog, including some experience with its object-oriented programming features, is essential. For engineers new to SystemVerilog the Doulos Comprehensive SystemVerilog course, or equivalent, is an essential pre-requisite.
For team-based courses, precursor training in SystemVerilog can be tailored to the team's specific profile using our Modular SystemVerilog portfolio. Contact Doulos to discuss options that suit your needs.
Course materialsDoulos course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:
- Fully indexed course notes creating a complete reference manual
- Lab files comprising the complete SystemVerilog source files and scripts
Structure and Content
IntroductionThe evolution of VMM from the VMM book through VMM 1.1 to VMM 1.2 • overview of the VMM testbench architecture • main features of VMM 1.2
Transaction CommunicationDefining transactions using vmm_data • shorthand macros • vmm_channel • the active slot • transaction completion models • TLM 2.0 communication • TLM ports and exports • analysis ports • sockets • the generic payload • VMM recommended guidelines
The VMM EnvironmentVirtual interfaces • clocking blocks • Using vmm_env • Using vmm_group • explicit phasing • implicit phasing • vmm_xactor • starting and stopping transactors • master and slave transactors • the atomic generator • running a test • programs
ConfigurabilityHierarchical name matching • searching object instances • class factory • factory overrides • callbacks • extending a callback fašade • registering callbacks • order of callback execution • configuration database • vmm_opts • configuration macros • setting a virtual interface • command line options
Messagingvmm_log • using the message service • built-in message macros • types and serverities • message handling • message catching • redirecting to a file • notifications • vmm_notify • indicate and wait_for • synchronization mode • notify callbacks • built-in notifications • using vmm_consensus • explicit vs. implicit consensus mechanism
The Datastream ScoreboardUsing the datastream scoreboard • overriding transform and compare • comparison modes • creating monitors • using TLM analysis exports • defining export implementations • handling multiple streams • using iterators
The Scenario GeneratorUnderstanding scenarios • vmm_scenario_gen • using the apply method • the scenario set • scenario identifiers • executing a scenario • using scenarios in tests • configuring scenario generators • using the configuration database with scenarios • creating hierarchical scenarios • single stream scenarios • multi-stream scenarios • registering channels with a generator • exclusive channel access
The Register Abstraction LayerThe RAL register model • RALF and ralgen • RAL-based environments • predefined register tests • register coverage
vmm_subenv and vmm_consensusReusing verification environments • using vmm_subenv • using vmm_group • scalable end-of-test mechanism • using explicit phasing • using implicit phasing • the memory allocation manager
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