SystemVerilog for New Designers
SystemVerilog as a first or second language for FPGA or ASIC design
(Previously known as SystemVerilog for FPGA/ASIC Design)
Standard Level - 4 days
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SystemVerilog for New Designers prepares the engineer for practical project readiness for FPGA or ASIC design, including RTL synthesis, block-level test benches, and FPGA design flows. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects. While the emphasis is on the practical SystemVerilog-to-hardware flow for FPGA devices, this training course also provides the essential foundation needed by ASIC and FPGA designers wishing to go on to use the advanced features of SystemVerilog for functional verification.
SystemVerilog for New Designers is suitable for delegates who are learning SystemVerilog as their first hardware description language. For teams who are already skilled in Verilog or VHDL, this training course can be offered in a shortened form for on-site delivery. For verification teams who are looking to use the class-based features of SystemVerilog for constrained random functional verification, Doulos provides Modular SystemVerilog for in-house training options.Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.
Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:
The course includes specific lab support for tool sets from the leading FPGA vendors including the vendor's native simulation and place-and-route tools.
The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.
What you will learn
- The SystemVerilog language concepts and constructs essential for FPGA and ASIC design
- How to write SystemVerilog for effective RTL synthesis
- How to target SystemVerilog code to an FPGA device architecture
- How to write simple and efficient SystemVerilog test benches
- The tool flow from SystemVerilog through simulation, synthesis and FPGA place-and-route
- How to write high quality SystemVerilog code that reflects best practice in the industry
- How to write re-usable, parameterisable SystemVerilog code by exploiting parameters
- How to run gate-level simulations
Who should attend?
Digital hardware design engineers who wish to learn how to use SystemVerilog for FPGA or ASIC hardware design at the register-transfer level (RTL) and for block-level verification.
Delegates should have a good working knowledge of digital hardware design, or have attended Essential Digital Design Techniques (or equivalent). No previous SystemVerilog or Verilog knowledge is required.
Doulos class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:
- Fully indexed class notes creating a complete reference manual
- Workbook full of practical examples and solutions to help you apply your knowledge
- Doulos SystemVerilog Golden Reference Guide for language, syntax, semantics and tips
- Tool tour guides (to support the tools and technologies used on the course)
Structure and content
IntroductionThe scope and application of SystemVerilog • Design and tool flow • FPGAs • Introduction to synthesis and synchronous design • SystemVerilog resources
ModulesModules • Ports • Continuous assignments • Comments • Names • Design hierarchy • Module instantiation • Port connection shorthand • Test benches • Simple procedures
Numbers and formattingNumbers • 2-valued & 4-valued logic • Vectors • Bit and part select • System calls • Output formatting • Time units • Always blocks • Ending simulation
Procedures - Event controls and Ifinitial & always • Event controls • if • begin & end • Combinational logic • always_comb • Incomplete assignment and latches • Unknowns and don't cares •
Procedures - Case and Loopcase • casez & casex • unique & priority • for • repeat • while • forever • break • continue • Integer variables
Clocks and Flip-flopsSynthesis of flip-flops and latches • Avoiding race hazards • Blocking & non-blocking assignments • Dealing with the scheduler and with clock skew • always_ff •Synchronous & asynchronous resets • Clock enables • Coding templates for synthesis • Flip-flop inference
Operators and NamesBitwise, logical, reduction, and equality operators • Concatenation • Replication • Conditional operator • Hierarchical names
MemoriesArray types • RAM coding style • Memory inference versus instantiation • $readmemb
Finite State MachinesState machines architecture • Coding styles for state machines • enum • State encoding • Unreachable states and input hazards
Types and PackagesInteger types • struct • packed • typedef • package • using • Scope resolution
Synthesis of Arithmetic and CountersArithmetic operators and their synthesis • signed & unsigned values • Resource sharing • Exploiting FPGA resources
File Organization and Parameterized ModulesCompilation units • Compiler directives • include • Macros • Conditional compilation • parameter • localparam • Parameter overriding • Parameterized modules • generate
Tasks and Functionstask • function • Argument passing • return • local declarations • automatic • Synthesis of tasks & functions
File I/OOpening & closing files • Reading & writing files • The $display family • Using $fscanf •
Interfaces and Clocking Blocksinterface • Interface ports • modport • clocking • Clockvars • Clocking drives • Avoiding scheduler problems
Gate-Level SimulationLibraries • SDF back-annotation • The DPI • force & release • Gate-level language constructs • Tristates & bus resolution
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