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SystemVerilog for New Designers prepares the engineer for practical project readiness for FPGA or ASIC design, including RTL synthesis, block-level test benches, and FPGA design flows. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects. While the emphasis is on the practical SystemVerilog-to-hardware flow for FPGA devices, this training course also provides the essential foundation needed by ASIC and FPGA designers wishing to go on to use the advanced features of SystemVerilog for functional verification.

SystemVerilog for New Designers is suitable for delegates who are learning SystemVerilog as their first hardware description language. For teams who are already skilled in Verilog or VHDL, this training course can be offered in a shortened form for on-site delivery. For verification teams who are looking to use the class-based features of SystemVerilog for constrained random functional verification, Doulos provides Modular SystemVerilog for in-house training options.

Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.

Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:

Simulation Aldec Active HDL™ & Riviera-PRO™ Cadence Incisive® Mentor Graphics ModelSim® & Questa® Synopsys VCS®

Synthesis Synopsys Synplify Pro® Synopsys Design Compiler® Mentor Graphics Precision® RTL

The course includes specific lab support for tool sets from the leading FPGA vendors including the vendor's native simulation and place-and-route tools.

The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.

What you will learn

• The SystemVerilog language concepts and constructs essential for FPGA and ASIC design
• How to write SystemVerilog for effective RTL synthesis
• How to target SystemVerilog code to an FPGA device architecture
• How to write simple and efficient SystemVerilog test benches
• The tool flow from SystemVerilog through simulation, synthesis and FPGA place-and-route
• How to write high quality SystemVerilog code that reflects best practice in the industry
• How to write re-usable, parameterisable SystemVerilog code by exploiting parameters
• How to run gate-level simulations

Who should attend?

Digital hardware design engineers who wish to learn how to use SystemVerilog for FPGA or ASIC hardware design at the register-transfer level (RTL) and for block-level verification.

Prerequisites

Delegates should have a good working knowledge of digital hardware design, or have attended Essential Digital Design Techniques (or equivalent). No previous SystemVerilog or Verilog knowledge is required.

Training materials

Doulos class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:

• Fully indexed class notes creating a complete reference manual
• Workbook full of practical examples and solutions to help you apply your knowledge
• Doulos SystemVerilog Golden Reference Guide for language, syntax, semantics and tips
• Tool tour guides (to support the tools and technologies used on the course)

Structure and content

Introduction

What is SystemVerilog? • History • Language Evolution • Language Features in SystemVerilog • Design Flow • Tools • SRAM-based FPGAs • SRAM FPGAs – Typical Logic Block • FPGAs – Extra Features • Typical Functional Simulation Flow • Typical Synthesis Flow • Recommended Design Style for Synthesis • Timing Constraints • Typical FPGA Implementation Flow • Timing Simulation & Download • Benefits of SystemVerilog • SystemVerilog Books • Verilog Resources • SystemVerilog Resources

Modules

Modules and Ports • Continuous Assignment • Rules and Regulations • Single-line vs Block Comments • Names • Reserved Identifiers • Internal connections • `default_nettype • Hierarchy • Port Connection Shorthand • Unconnected Ports • Test Fixtures • Outline of Test Fixture for MUX2 • Initial Blocks • Variables • $monitor • The Complete Test Fixture • Introduction to Tcl Scripts • A Tcl Example

Numbers and Formatting

Logic Values • 4-state Integer Types • 2-state Integer Types • 2-State and 4-State Values • Vectors • Numbers • Truncation and Extension • Signed Numbers • “Disguised” Binary Numbers • More than 32 bits • Formatted Output • Formatting • Formatting Text • Timeunit and Timeprecision • Formatting Time Values • $timeformat • Always • $stop and $finish • Default time units

Always Blocks

RTL Always Statements • Sensitivity List for Combinational Logic • always_comb • If Statements • Begin-End • Else If • Nested If and Begin-End • Incomplete Assignment • FPGAs and Transparent Latches • X • Unknown and Don't Care • Conditional Operator • Unknowns in Conditionals • Parallel Procedural Assignments • Parallel Continuous Assignments • Tristates

Procedural Statements

Case Statement • Case Statement Continued • Casez Pattern Matching • Casex Pattern Matching • Casez and Casex Truth Tables • Priority Encoder Using Case • Full and Parallel Case Statements • Careless Casez • Unique and Priority Case • One-Hot Decoder Using Case • Unique If • Loop Statements • SystemVerilog for loop • For Loop Synthesis • For Loop Variable Declaration • do...while, break, and continue • Loops in Test Fixtures • Local Variables • Labeling • Disable • Combinational Always

Clocks and Flip-flops

Edge Triggered Flip-Flop • Avoiding Simulation Races • The SystemVerilog Scheduler • Blocking, Non-blocking, and #0 • Nonblocking Assignments • Asynchronous Set or Reset • Synchronous vs Asynchronous Actions • Clock Enables • iff • Synthesis Templates • RTL Synthesis Tool Architecture • RTL Synthesis • Creating Flip-Flops • Flip-flop Inference - Blocking Assignment • Flip-flop Inference - NonBlocking • • Flip-Flop Merging • No Flip-Flop Optimization • Optimized by Hand

Operators and Names

Bitwise and Reduction Operators • Logical Operators • Equality Operators • Equality between Vectors • Part Selects • Indexed Part Select • Concatenation • Shift Registers • Shift Operators • Replication • Summary of Operators • Beware++ • Hierarchical Names • Upwards Name References

Memories

Packed and Unpacked Arrays • Indexing Array Elements • Array Layout • Array Operations • Array Copying • Packed Arrays as Integers • Array Querying Functions • $bits • Packed Arrays and Concatenation • Braces in SystemVerilog • Unpacked Array Initialization • Default • Memories and Synthesis • Memories • RAMs • Instantiating Memories • Loading Memories

FSM Synthesis

Finite State Machines • State Transition Diagrams • Enumerations • Type-Checking of Enumerations • Overriding the Default Values and Type • Default Value of an Enum Variable • Various Rules for Enumerations • Explicit State Machine Description • State Machine Architecture • Timing in a Synchronous Design • Separate Output Decoding • Separating Registers from C-logic • No Output Decoding • One-Hot Using Case • State Encoding • Unreachable States • Controlling Unreachable States

Types and Packages

4-state and 2-state Types • Initial Values • Examples • Caveats with Signed Types • Enumerations, Arrays, typedef • struct • typedef struct • Packed Struct • Packed Union • Multidimensional Arrays • Odds and Ends • Nets, Ports and Data Types • Concurrent Assignment to a Net • Variables and Data Types • Concurrent Assignment to a Variable • Packages • Packages and Ports • Packages – Another Example

Arithmetic

Synthesis of Arithmetic Operators • Vector Arithmetic • Signed Types • Behaviour of Signed Types • Unsigned versus Signed • Arithmetic Expressions • Arithmetic Examples • Integer and Synthesis • Arithmetic Operators • Choice of Adders • Arithmetic Isn't Optimised • Arithmetic WYSIWYG • Resource Sharing

File Organisation and Parameters

Compilation • Compilation Units • Declarations Outside Modules • Compile Options • SystemVerilog Preprocessor • `define and `include • `ifdef • Enhanced Conditional Compilation • Parameters • Overriding Parameters • localparam • using Parameters • generate • generate for • generate if • generate case

Interfaces

Introduction to Interfaces • APB with Master and Single Slave • Why Not Use a Struct • Interface • Using an Interface • Accessing Interface Members • Modports • Modport Directions • Connecting Ports using Modports • Interface Ports and Parameters • Synthesis Example • Synthesis Results • Imported Functions for Design • Implementation • Multiple Drivers on a Bus • Bus Readback Challenges • Modport Expressions • Modport Expressoins and Generate • Generate the Attached Modules • Applications for Interfaces

Tasks and Functions

Tasks • Calling (Enabling)) a Task • Task Arguments • Task Argument Passing • Static versus Automatic Storage • Other Task Features • ref arguments • Functions • Task vs. Void Function • Synthesisable Functions • Synthesis of Tasks • Calling RTL Tasks

File I/O

Modeling the Test Environment • System Tasks for Output • $strobe • Writing to Files • Opening and Closing Files • File Modes • Reading From a File – Formatted Data • Formatting the Data for $fscanf • $fscanf • Strings • String Operations • String Methods • $sformat and $sformatf • Reading a File Line By Line • Diagnosing File I/O Errors • Immediate Assertions • File I/O – Summary

Gate Level Simulation & C Interfacing

Basic Design Flow • Why Simulate the Gates? • Verilog Flow for PLD Design • Design Flow for ASIC Design • "Classic" Verilog Libraries • Comparison On-the-fly • Direct Programming Interface (DPI) • DPI Simulation Flow • Importing C Functions • C Function Name and Arguments • Exporting Functions to C • DPI: Mapping Data Types • Scalar Bit and Logic Values • Packed Arrays • Other Types • Arguments and Return Values