Intensive SystemVerilog and UVM
Accelerated SystemVerilog and UVM training for verification teams (on-site only)
Standard Level - 5 days
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Intensive SystemVerilog and UVM offers an accelerated learning program for on-site training where a verification team commits to learn both SystemVerilog and UVM in a single 5-day training class.
In teaching SystemVerilog, Intensive SystemVerilog and UVM focusses on the aspects of SystemVerilog that are needed to learn and use UVM, particularly the class-based verification features. In teaching UVM, it focusses on the essentials necessary to get a first practical UVM verification environment up-and-running.
This intensive class offers an alternative to the standard learning path for SystemVerilog and UVM from Doulos, which comprises either SystemVerilog for Verification Specialists (4 days) or Comprehensive SystemVerilog (5 days) followed by the UVM Adopter Class (4 days from June 2013). Since the content from 8 or 9 days of training is being delivered in just 5 days, this class represents a compromise that is best suited to verification teams who already have some prior experience with verification languages or object oriented programming.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.
Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported for this course include:
- Aldec Riviera-PRO
- Cadence Incisive®
- Mentor Graphics Questa®
- Synopsys VCS®
Other tools may be available on request. Please contact Doulos if your preferred tools are not listed here.
Who should attend?
- Verification teams wishing to learn both SystemVerilog and UVM in a single, intense 5 day training class.
- Verification teams wanting to migrate to SystemVerilog and UVM from other verification languages and methodologies.
What will you learn?
- SystemVerilog Fundamentals lays the foundations for learning the SystemVerilog language for verification by introducing the essential language features.
- Class-Based SystemVerilog teaches the features of SystemVerilog necessary to build a UVM class-based verification environment, which includes the features needed to support a constrained-random, coverage-driven verification methodology. There is also a brief introduction to SystemVerilog Assertions.
- Applying UVM builds on the previous days as it introduces the specific features of the UVM base class library.
Pre-requisitesA good working knowledge of Verilog is essential. Some previous experience with SystemVerilog is preferred, though not essential. Previous experience with another verification language or object-oriented programming language (e.g. Vera, e, C++, SystemC) is highly desirable and will ensure an acceptable learning outcome.
Due to the intensive nature of this class, it is not possible to combine Verilog training with Intensive SystemVerilog and UVM training in the same week. Please contact Doulos to discuss the options.
CaveatThis is an intensive course that is aimed at teams who already have verification experience using another similar language. It is not suitable as an introduction to SystemVerilog or UVM for engineers coming directly from an HDL background, for whom Comprehensive SystemVerilog followed by the UVM Adopter Class would be more suitable.
Training materialsDoulos class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:
- Fully indexed class notes creating a complete reference manual
- Workbook full of practical examples and solutions to help you apply your knowledge
- Doulos SystemVerilog Golden Reference Guide for language, syntax, semantics and tips
- Doulos UVM Golden Reference Guide
Structure and Content
SystemVerilog Fundamentals (Day 1)
IntroductionWhat is SystemVerilog? • Language Evolution • SystemVerilog versus Verilog • Reg, Logic, and Bit • Variables, Wires, and Ports • SystemVerilog Language Features • Caveats • The UVM Family Tree • Books and Resources
Programming Language FeaturesC-Like Language Features • Static vs Automatic Variables • Static vs Automatic Tasks • ++, --, and Assignment Operators • Labeling • Time Units • Do While Loop • Enhanced Tasks and Functions • Task and Function Arguments • Void Functions • Argument and Return Types • Type string • $sformatf
Basic Data Types4-state and 2-state Types • Caveats with Signed Types • Initial Values • Every variable and wire has a well-defined initial value • Enumerations • Type-Checking of Enumerations • struct • typedef struct • Packed Struct • Packed and Unpacked Arrays • Indexing Multidimensional Arrays • Packages • Packages and Ports
InterfacesModelling a Bus • APB with Master and Single Slave • Modelling APB using Ports • Simple Interface = Bundle of wires/vars • Using an Interface • Accessing Interface Members • Modports • Modport Directions • Connecting Interfaces with Modports • Generic Interface Ports • Ports and Parameters to Interfaces
Clocking BlocksInput and Output Skew • Creating a Clocking Block • Testbench and Clocking Block • Cycle Delays and Clocking • Input and Output Skew Syntax Summary • Scheduler Regions • Stimulus and Response • Signal Aliasing • Multiple Clocking Blocks • Driving a Net • Clocking Blocks in Interfaces • Clocking Blocks versus Programs
Arrays and QueuesDynamic Arrays • Queues • Working with Queues • Queue Methods • Associative Arrays • Associative Array Methods • Foreach
Class-Based SystemVerilog (Days 2-3)
Classes for TransactionsConstrained Random Verification • Representing Transaction Data • SystemVerilog Classes • Object = Instance of Class • Initializing Objects • Constructor Arguments • Static Data Members • Constant Data Members • Randomized Data Members • Data Members of Class Type • Forward Typedef • Object Copy with new • Shallow Copy • Deep or Shallow Copy?
Virtual InterfacesTest Harness and Testbench • Modules versus Classes • Creating the Testbench • Virtual Interface • Building a test harness • Adding a clocking block • Virtual interface • Connecting the virtual interface • Accessing a Task through a Modport • Testbench Static Structure • BFM or Driver Class • Testbench Object Structure
Extending Classes for StimulusImproved Generator Class • Constrained randomization • Creating an Extended Class • The Inheritance Relationship • Inheriting Class Members • Jargon • Control Knobs and Constraints • Methods of Extended Class • Derived-class Object, Base-class Variable • Virtual Methods • General-Purpose Infrastructure
TLM and ChannelsReusable Verification Environments • Transaction Level Modelling • Using Channels • Generic Channel and Transaction Classes • Out-of-Block Declarations • Connecting Channel • Getting Data from a Generic Channel • Safe Downcasting with $cast • Type Parameterization of Classes • Running Components with fork...join • fork...join_none • Identifying Forked Processes
Component HierarchyTestbench Component Hierarchy • Implementing Relationships • Base Classes (review) • Abstract Class and Pure Virtual Methods • Component Base Class • Launching a Task with fork...join_none • Customising a Component • Constructing a Component
Functional CoverageCoverage Driven Verification • Verification Planning • From Features to Tests • Covergroups • Embedded Covergroups • Procedural Sampling • Arguments and Options • Coverage Bins • Cross Coverage • Cross Coverage and Labels • Cross Coverage Example • Controlling Cross Bins • Transition Coverage
More on ConstraintsInline Constraints • Overriding Constraints • Procedural Control of Randomization • Procedural Control of Constraints • Constraint Ordering • Function Calls within a Constraint • Constraining Dynamic Arrays • Constraining an Array-of-Objects • Arrays within a Constraint • Hierarchical Constraints
SystemVerilog AssertionsProperty versus Assertion • Immediate and Concurrent Assertions • Action Blocks and Severity • Concurrent Assertions • Temporal Behaviour • Clocks and Default Clocks • |=> and |-> • $past • Sequences • Concatenation and Repetition • Simulation of Assertions
Applying UVM (Days 4-5)
Introduction to UVMThe Universal Verification Methodology • The UVM Open Source Standard • UVM Highlights • Tests versus Testbench • Configurable Verification Components • UVM Class Hierarchy • UVM Basic Simulation Phase Methods • Alternative Run Phases • Phase Synchronization • Customization - The Factory • TLM Connections • Required / Provided Interfaces • Push vs Pull Connections • Layered Sequential Stimulus • Virtual Sequences • Learning and Using UVM
Getting Started with UVMSimple Testbench Architecture • Sequence Item Class • Methods of a Transaction Class • Overriding do_compare • Alternative - Field Macros • Sequence Class • Alternatives: Do Macros or Function Calls • Objections • Driver • Driver run_phase Task • Simple Testbench Architecture • Environment - Constructor • Environment - Build Phase • Environment - Connect Phase • Configuration Database • DUT Interface • The Config Database • Connecting the Virtual Interface • Test Class - build_phase • Test Class - run_phase • Top-Level Module • Running a Test
Writing TestsEasier UVM Coding Idioms • Starting a Sequence from a Test • Wildcard Searches • Nested Sequences • Child Sequence • Child Sequence Body • Parent Sequence • p_sequencer • Sequence Macros • From the Driver's Side • Sequence-Driver Interaction • Configuration • Creating a Configuration Object • Getting the Configuration Object • Extending an Existing Class • Factory Overrides • Selecting the Test from the Command Line
Monitors, Reporting, and TLMDriver versus Monitor • Monitor Class • Monitor Run Task • Reporting • Report Macros • Controlling Verbosity • Setting Actions • Severity and Actions • Scope of Actions • Writing to a Log File • The Reporting Set Methods • TLM Ports, Exports, and Imps • Port-Child Port Binding • Export-Child Export Binding • Implementing an Export • Monitor with Devolved Tasks • Analysis Ports • Monitor with Analysis Port • Subscriber • Registering Subscribers
Checkers and ScoreboardsExample Design • Separating Test from Test Harness • Interfaces • Modports • Bus Cycles • Bus Properties • Adding ISS Reference Model • Sampling Bus in Interface • Bus Monitor Class • Detecting Bus Sequence • Bus Monitor run Task • ISS • Verification Environment • Scoreboard • Comparator Input Requirements • Field Macros • Field Macro Flags • Overriding do_compare • Field Macros and Overridden Methods • Overriding do_pack • Redirecting Reports
Functional Coverage & End-of-TestCoverage Collection • Detecting States in Bus Monitor • Embedded Covergroups in UVM • Plumbing the Coverage Collector Class • Analysis Subscriber Classes • TLM imp Macros • Coverage on Internal States of DUT • Objection Mechanism • Raising and Dropping Objections • Objections in Sequences • Objection Drain Time
Configuring the TestbenchConstrained Random Generation • Factory Overrides "By Name" • Regular Expressions and Globs • Parameterized Components • The Configuration Database • Verilog / VHDL versus UVM • Setting Configuration Table Entries • Getting Configuration Table Entries • Multiple Configuration Tables • Debugging Configuration Settings • Configuration Objects • UVM Command Line Processor • Standard Command Line Arguments
Agents and Virtual SequencesAgent Architecture • UVM Agent • Agent Build • Connecting Agent Components • Configuring an Agent • Starting a Sequence Automatically • Virtual Sequences and Sequencers • Virtual Sequence • Starting Virtual Sequence from Test
More on SequencesSequence Callbacks • Virtual Sequences Revisited • Locking a Sequencer • Calling Lock/Grab • Request and Response • Pipelined Responses in the Sequence • Pipelined Responses in the Driver • Reponses with Layered Sequencers • Layering Sequences and Agents • The Layering Sequence • Multiple Agents / Sequencer Stacks • Transaction Recording • Reports within Sequences
Appendix (extra topics for reference)The Report Catcher • Registering Report Catchers • Blocking put, get, and peek • Blocking versus Non-Blocking Methods • uvm_tlm_analysis_fifo • Subscriber with uvm_tlm_analysis_fifo • Subscriber with FIFO Implementation • Stopping a Test - OVM Legacy • Barriers and Barrier Pools • Setting the Threshold • UVM Tests and DUT Registers • UVM Register Layer • Register Block & Address Map • A Register Sequence • User-Defined Register Test • UVM Simulation Output
This course is available for team training only
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