Monday 25 September 2017

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Expert VHDL

Learning PathAdvanced Level - 5 days

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 Auf Deutsch

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Expert VHDL is an intensive 5-day advanced application class. It teaches engineers how to increase productivity by enhancing their VHDL coding and application skills. Presented in two distinct course modules, Expert VHDL focuses on language and synthesis issues, design maintainability and re-use, test benches and the latest techniques for verification - including an introduction to OVL/PSL and modern assertion-based approaches to verification.

  • Expert VHDL Design (2 days) is for design engineers wishing to deepen their knowledge of RTL synthesis using VHDL, and to improve their VHDL coding style with design maintainability and re-use in mind. Design for Verification is also covered with an introduction to modern assertion-based techniques.

  • Expert VHDL Verification (3 days) is for design engineers and verification engineers involved in VHDL test bench development or behavioural modelling for the purpose of functional verification

The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.

Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:

    Simulation
  • Aldec Active HDL™ & Riviera-PRO™
  • Cadence Incisive®
  • Mentor Graphics ModelSim® & Questa®
  • Synopsys VCS®
    Synthesis
  • Synopsys Synplify Pro®
  • Synopsys Design Compiler®
  • Mentor Graphics Precision® RTL

The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.

Who should attend?

  • Design engineers wishing to improve the efficiency of their hardware designs and increase productivity
  • Design and verification engineers who want to structure and write effective test environments to verify complex designs and systems

What will you learn?

  • A set of VHDL language features that go beyond what is taught on a basic training class
  • A deeper understanding of the VHDL language and how to apply it, enabling you to troubleshoot VHDL simulation and synthesis problems with ease
  • The principles and details of how to approach the problem of design verification using VHDL
  • How to structure and write large and complex VHDL test benches
  • The principles and details of how to write behavioural models of hardware components in VHDL
  • To produce smaller and faster hardware design using VHDL and RTL synthesis tools
  • A solid introduction to the topic of behavioural synthesis from VHDL, enabling you to judge the applicability and effectiveness of behavioural synthesis in your design context
  • The details of a VHDL coding style to facilitate code re-use and how to package IP for re-use
  • An introduction to IEEE 1076-2007c (VHPI) and the proposed VHDL 2008

Pre-requisites

This is an advanced language and methodology training class. Prior attendance of the Doulos Comprehensive VHDL class (or equivalent) is required, and at least 6 months of 'live' project experience using VHDL is strongly recommended. Delegates attending the Expert Design module must have knowledge and experience of register transfer level coding and synthesis using VHDL

Training materials

Doulos training materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Class fees include:
  • Fully indexed class notes creating a complete reference manual
  • Workbook full of practical examples to help you apply your knowledge
  • Doulos Golden Reference Guide for language, syntax, semantics and tips
  • Tour guides (to support the tools and technologies of your choice).

Structure and Content

Expert VHDL Design (Days 1-2)


RTL Synthesis and Synchronisation

Synchronous Design • Synthesis of combinational and sequential logic • Variables in clocked processes • How Many Registers? • Synchronous Design Rules • Static Timing Analysis • Non-Synchronous Features • Timing Analysis Exceptions • Asynchronous Inputs • Input Hazard • Metastability • Synchroniser in VHDL • Multiple Clock Domains • Transferring Data Between Clock Domains • Using a FIFO for Synchronisation • Controlling a Flag from Two Clock Domains • Clock Divider in VHDL • Clock Divider Timing • Synchronising Reset • Re-timing and Pipelining • Hierarchy and Optimisation • Registered Ports

Introduction to VHDL 2008 (Design)

Status of VHDL 2008 • Overview of VHDL 2008 • "Convenience" Features • Example (Design) • Changes to port maps • Major Changes in VHDL 2008 • New Packages • Extended Generics • Generics on a Package • Type Generics • Subprogram generics • VHDL 2008 Operators • VHDL 2008 Types • Statements

Writing Readable Designs

VHDL Features for Abstraction • Record Types • Using Record Fields • Aggregates • Using Records for Wiring • Connecting Records • Inside a Peripheral • Multiplexed Bus Structure • Multiplexing Records • Representing Register Maps • Accessing Individual Registers • Accessing the Status Register • Collecting Registers Together • Alias • Using Aliases with Vectors • Using Alias with a Bus • Other Uses of Alias • • Named Ranges

Writing for Synthesis

Using NUMERIC_STD • Numeric_std and Std_logic_vector • Conversions • Summary of NUMERIC_STD • Arithmetic WYSIWYG • Eliminating the Mux • Forcing an Implementation • Inference or Instantiation? • Synthesis Attributes • How Clever is Your Synthesis Tool? • Resource Sharing • Eliminating Loop Dependencies • Multiple Drivers • Tri-state Inference • Clocked Tri-states • Dynamic Indexing • Handling Unknowns • Don't Cares • STD_MATCH • One-Hot Decoding

Writing For Re-Use

Re-use Tradeoffs • A Universal Re-use Methodology? • Language-Level Re-use • Reusing Code Fragments • Standard Component Re-use • IP Deliverables • Writing Re-usable RTL IP • Example of a Regular Structure • Regular Ports • Types and Subtypes • Using Generics • Parameterised Ports • Array Attributes • Parameterising Ranges • Unconstrained Array Ports • Regular Implementation Structure • Using Generate • Parameterised Regular Implementation • Generate or Loop? • Generating Instances • Generating Attribute Values • Regular Output Logic • Parameterised Output Logic • More Multiple Driver Issues • Longest Static Prefix • Optional Ports • Default On Component • Component Libraries

Advanced Coding Styles

Subprograms • Procedures • Destructive Register Reads • Read Procedure • Functions • Subprograms in Packages • Recursion • Recursive Function Example • Creating a Generic Counter • Recursive Instantiation • Recursive Component Declaration • Solving the Problem • Recursion - Synthesis Results • Arrays of Arrays • Multidimensional Arrays • Flattening Matrices • Re-use Revisited • Multidimensional Arrays of Ports • Getting and Setting Rows • Architecture Using 2D Arrays • Instancing The Design

Finite State Machine Synthesis

State Transition Diagrams • Finite State Machines • Two Process State Machine in VHDL • Timing in a Synchronous Design • One Process State Machine Description • State Machine Architecture • Comparison of Coding Styles • Separate Output Decoding • Easier Registered Outputs • Registered Outputs Using Local Variables • State Encoding • Unreachable States • Controlling Unreachable States • No Output Decoding • Explicit One Hot Style • Hand Optimised One Hot Style • Collision Signal • Too Many States?

Expert VHDL Verification (Days 3-5)


Functional Verification

What Is Verification? • Approaches to Verification • Verification Strategy • What to Verify? • Towards a Verification Plan • Don't Plan Everything • Identify Testcases • Verification Metrics • Coverage • • Including Functional Coverage • Coverage Driven Verification • From Features to Tests • Checking • Verification Planning Revisited • The Basic Testbench • Verification Environment • Verification Methodologies • VHDL Methodology • Verification Resources • Design for Verification • Glass Box Testing • Analysis to Choose Tests • Boundary Conditions & Corner Cases • Analysis to Choose Tests • Black Box Testing • Regression Testing • Stress Testing • Different Sorts of Stimulus • Random Stimulus • Constraining Random Stimulus • Random Sequence of Valid Actions • Checking Results

Subprograms

Using Abstraction in a Testbench • Procedures • Parameter Class, Mode, and Type • Functions • Subprograms in Packages • Signal Parameters • Subprogram Overloading • What is a (VHDL) Transaction? • Wait Statements and Time

Vector Based Testing

The Basic Testbench • TEXTIO Output • Opening and Closing Files • TEXTIO Input • Testing the File Open Status • Managing Text Files • Procedure READ • When READ Goes Wrong • Package STD_LOGIC_TEXTIO • Converting Values to Text Strings • Checking Expected Results • Using Built-in Files • Reading Variable Length Data • Files Without Textio • Binary Files • Testbench Start • Stopping A Testbench

Comparing Models

Comparing Results • Configuration • Default Configuration • Hierarchical Configurations • Nested Configurations • Checking RTL Vs. Gate Level • Sampling Data - RTL • Postponed Processes • Sampling Data - Gate Level • Interfacing Design Entities • Type Conversions • Strength Strippers • VHDL Netlist • Simulating the Netlist • VHDL Configuration • Using a Signature Register • Signature Analysis • Signature Analysis Improvements

Time In Testbenches

Inspecting the Event Queue • Example SRAM Timing • Setup Time Check • Hold Time Check • Combined Setup / Hold Time Check • Pulse Width Check • '0' to '1' Change • Entity Declarations • Passive Processes • Using Vital Packages • Setup/Hold Check With Vital • What About Transactions? • Concurrent Signal Assignments • Drivers • How to "See" Drivers • Sequential Signal Assignments • Inertial Delay • Identical Successive Assignments • Transport Delays

Coping With Latency

Variable Latency • Record Types • User Defined Array Types • Arrays of Records • Queues • VHDL Queue Implementation • Using Queues • Coping with Out-of-Order Completion • Scoreboarding • Shared Variables • Impure functions • Protected types • Protected type body • Declaring a Shared Variable

Properties and Assertions

Property versus Assertion • Applying Properties • Who Writes Properties? • Observability • A Simple Assertion • Simulation Checker or Monitor • Properties and the Specification • OVL • Using OVL with VHDL • OVL Packages • OVL Configuration • Instancing an Assertion • OVL VHDL Assertions • Example Assertions • PSL • The Elements of a Property • PSL Basics • The Structure of PSL • The Boolean Layer • Clocks and Default Clocks • Holds and Implication • next • The Temporal Layer • The Verification Layer • Verification Units • Modelling Layer • Using PSL with an HDL • Simulation of Temporal Properties • Summary of Benefits

Modelling Techniques

Modelling Components • Behavioural Modelling Example • Modelling the 2-wire Bus • Model Structure • Two Wire Slave Model • Protocol Implementation • Data Generation • Slave Procedure • Modelling State • A/D and D/A Models • Sampled Analogue Circuits • Dynamic Memory Allocation • Access Types • Allocators • Deallocating Memory • Writing to a FIFO • Reading from a FIFO • Pointer Problems

Transaction Level Verification

Structuring Testbenches • Transaction Level Testcase • Making a Transaction in VHDL • Communicating Transactions • A Simple Example • Generating Transactions • Using Procedures with Signals • A Systematic Approach • Non-blocking Procedures • Bus Functional Modelling • Interfacing Without Events • Bus Functional Model • Bus Functional Model Using get • Synchronization • Synchronization Channel • Synchronization Channel Details

Testbench Architecture

Verification - Reminder • Completing our Methodology • Monitoring Internal Signals • The Objection Mechanism • Implementing Objection • Run-time Configuration • Path Name • Implementing Run-time Configuration • Functional Coverage • Coverage Using Concurrent Procedures • Coverage Procedure • Calling Coverage Procedures • Why Use Path Parameter? • Verification Recommendations • Package Useful Functionality • Build the Complete Testbench • Monolithic Testbenches are Inflexible • Hide DUT Interface from Testcase • Layered Architecture • Interface Between Layers • Separate Top-Level Entities • Creating Multiple Instances

Appendix - Co-simulation

Embedded Systems • Logic Simulation • Instruction Set Simulation (ISS) • Native Compiled Software • Co-simulation Tools • Simulating Software Execution • Modelling Memory Systems • Synchronisation • Requirements for ISS • Hardware/Software Co-simulation Benefits • Foreign Language Interfacing • Requirements of a FLI • FLI Implementation • Interfacing to a C program • Foreign Architecture • Foreign Subprograms • Foreign Architecture Example • VHPI Example • VHPI Callback • VHPI Elaboration Code

Appendix - Advanced VHDL Language

Run-time Configuration Example • User API • Protected Type Declaration • Deferred Constants • Protected Type Body • getConfigInfo "Helper" Function • Text Processing • Protected Type Method • Avoiding Protected Types • Modified tbpack • A further simplification

Appendix - Introduction to VHDL 2008 (Verification)

Status of VHDL 2008 • Overview of VHDL 2008 • "Convenience" Features • Example (Design) • Example (Verification) • Improved IO • Changes to port maps • Major Changes in VHDL 2008 • New Packages • Extended Generics • Generics on a Package • Type Generics • Subprogram generics • VHDL 2008 Operators • VHDL 2008 Types • Statements



Course Dates:
November 13th, 2017 Munich, DE Enquire
November 20th, 2017 Paris, FR Enquire
November 27th, 2017 Ringwood, UK Enquire
November 27th, 2017 Columbia, MD Enquire
November 27th, 2017 Ankara, TR Enquire
December 4th, 2017 San Jose, CA Enquire
December 11th, 2017 Marlborough, MA Enquire
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