Expert VHDL Verification
(including OSVVM & UVVM)
Advanced Level - 3 daysview dates and locations
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Expert VHDL Verification is an intensive advanced application class. It teaches engineers how to increase productivity by enhancing their VHDL coding and application skills. The syllabus focuses on test benches and current techniques for verification such as Transaction Level Verification (TLV) and also introduces the OSVVM and UVVM methodologies.
Carefully designed workshops comprise 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.
Expert VHDL Verification forms the last 3 days of the 5-day Doulos Expert VHDL class.
Who should attend?Design engineers and verification engineers involved in VHDL test bench development or behavioural modelling for the purpose of functional verification
What will you learn?
- A set of VHDL language features that go beyond what is taught on a basic training class
- The principles and details of how to approach the problem of design verification using VHDL
- How to structure and write large and complex VHDL structured verification environments
- The OSVVM and UVVM VHDL verification methodologies
Pre-requisitesTo maximise the training value, prior attendance of the Doulos Comprehensive VHDL (or equivalent) class is required.
Training materialsDoulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
- Fully indexed class notes creating a complete reference manual
- Workbook full of practical examples to help you apply your knowledge
- Doulos VHDL Golden Reference Guide for language, syntax, semantics and tips
- Tour guides (to support the tools and technologies of your choice)
Structure and Content
What Is Verification? • Approaches to Verification • Verification Strategy • What to Verify? • Towards a Verification Plan • Don't Plan Everything • Identify Testcases • Verification Metrics • Coverage • Including Functional Coverage • Coverage Driven Verification • From Features to Tests • Checking • Verification Planning Revisited • The Basic Testbench • Verification Environment • Verification Methodologies • VHDL Methodology • Design for Verification • Glass Box Testing • Analysis to Choose Tests • Boundary Conditions & Corner Cases • Black Box Testing • Regression Testing • Stress Testing • Different Sorts of Stimulus
Using Abstraction in a Testbench • Subprograms • Procedures • Parameter Class, Mode, and Type • Subprogram Overloading • Signal Parameters • Functions • Subprograms in Packages • Impure functions • Protected types • Protected type body • Declaring a Shared Variable
More on File IO
The Basic Testbench • TEXTIO Output • Procedure READ • When READ Goes Wrong • Converting Values to Text Strings • Opening and Closing Files • Testing the File Open Status • Managing Text Files • Package STD_LOGIC_TEXTIO • Using Built-in Files • Reading Variable Length Data • Files Without Textio • Binary Files • VHDL-2008 File IO
Transaction Level Verification
Structuring Testbenches • Build the Complete Testbench • Monolithic Testbenches are Inflexible • Hide DUT Interface from Testcase • Layered Architecture • Transaction Level Testcase • Making a Transaction in VHDL • Accessing the Fields • Communicating Transactions • A Simple Example • What is a (VHDL) Transaction? • Interfacing Without Events • Generating Transactions • Using Procedures with Signals • A Systematic Approach • Non-blocking Procedures • Bus Functional Modelling • Bus Functional Model • Bus Functional Model Using Get • Synchronization • Synchronization Channel • Summary
More on BFMs - Time in Testbenches
Bus Functional Modelling • Wait Statements • Wait Statements and Time • Inspecting the Event Queue • Example SRAM Timing • Setup Time Check • Hold Time Check • Combined Setup / Hold Time Check • Pulse Width Check • Entity Declarations • Passive Processes • Using Vital Packages • Setup/Hold Check With Vital • What About Transactions? • Concurrent Signal Assignments • Drivers • How to "See" Drivers • Multiple Driver Issues • Longest Static Prefix • Sequential Signal Assignments • Inertial Delay • Identical Successive Assignments • Inertial Delays • Inertial and Transport Delays • Sampling Data - RTL • Postponed Processes
Behavioral Modelling and Checkers
Checking Results • Variable Latency • Arrays of Records • Queues • VHDL Queue Implementation • Using Queues • Coping with Out-of-Order Completion • Scoreboarding • Dynamic Memory Allocation • Access Types • Allocators • Deallocating Memory • Writing to a FIFO • Rrading from a FIFO • Pointer Problems • Behavioural Modelling Example • Modelling the 2-wire Bus • Two Wire Slave Model • Protocol Implementation • Data Generation • Slave Procedure • Modelling State
Random Testing and Coverage
Verification - Reminder • Random Stimulus • Constraining Random Stimulus • Random Sequence of Valid Actions • Functional Coverage • Where Am I? • Concurrent Procedures • Coverage Procedure • Calling Coverage Procedures • Why Use Path Parameter?
Other Testbench Features
Completing our Methodology • Monitoring Internal Signals • Monitoring Internal Signals - VHDL-2002 • External Names • Monitoring Internal Signals - VHDL-2008 • Force and Release • The Objection Mechanism • Implementing Objection • Resolution Functions • Implementing Custom Objections • The Stop and Finish Procedures • Run-time Configuration • Implementing Run-time Configuration
Introduction to OSVVM
What is OSSVVM? • Randomization • Seed Management • Functional Coverage • Sampling • Specifying Bins • Specifying a Minimum Hit Count Per-Bin • Specifying Cross Bins • Specifying Ignore Bins • Displaying Coverage • Non-Repeating Randomize • Defining Explicit Weights • Weight by Coverage Shortfall • Logging • Redirecting to a Log File • Alerts • Stop Count • Disabling Alerts • Conditional Alerts • Hierarchical Alerts • Other Packages
Introduction to UVVM
What is UVVM? • Utility Library • Logging and Verbosity Control • Outputting Log Messages • Controlling Log Messages • Message IDs • Redirecting Log Messages • Alerts • Controlling Alerts • Reporting Alerts • Checks • Awaits • String Handling • Randomization • Signal Generators • Synchronization • BFM Common Package • Warnings • UVVM VVC Framework • UVVM Structure • UVVM Test Harness • UVVM Test Bench • Test Sequencer • UVVM Command Distribution • Example Command Distribution Methods • UVVM VHDL Network Model • VIP • Feature Comparison
|November 28th, 2018||Heesch, NL||Enquire|
|December 19th, 2018||Munich, DE||Enquire|
|February 13th, 2019||Ringwood, UK||Enquire|
|February 20th, 2019||Munich, DE||Enquire|
|February 27th, 2019||Columbia, MD||Enquire|
|May 15th, 2019||Boston, MA||Enquire|
|June 5th, 2019||Munich, DE||Enquire|
|June 19th, 2019||Ringwood, UK||Enquire|
|July 10th, 2019||Ankara, TR||Enquire|
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