Verification Methodology Manual (VMM)
What is VMM ?
The VMM verification methodology for SystemVerilog enables engineers to build powerful and robust verification environments for complex electronic systems and IP. IP created according to the VMM methodology allows for easy "plug-and-play" use in VMM testbenches, and engineers with VMM expertise can quickly create or enhance their verification environment without having to spend time learning or developing a non-standard methodology.
The VMM is defined in the Verification Methodology Manual (VMM) for SystemVerilog, a professional book co-authored by verification experts from ARM Ltd and Synopsys Inc. The VMM contains a wide-ranging set of rules and recommendations for constructing testbenches and test suites, for the use of assertions in verification, for making use of legacy testbench code and for system-wide verification strategy.
In May 2008, Synopsys donated its complete implementation of the VMM to Accellera to enable verification interoperability standardization.
Doulos has been continuously engaged with VMM-based verification since its release in 2005, and has been delivering SystemVerilog training and client support since 2004. This has included co-operation with key verification methodology developers at Synopsys, and resulted in availability of the world's first independent VMM training from Doulos in 2007.
The latest release of this class, the VMM Adopter Class, is an integral part of the Doulos SystemVerilog out of the Box™ program and joins the Doulos range of SystemVerilog training and support components. More >>
Since 2004, Doulos has amassed a bank of VMM and SystemVerilog experience and expertise across all industry segments and tool contexts. In 2006, some of this know-how was distilled in the VMM Companion Guide, which you can download here>>.
Doulos has also presented award winning VMM papers at DVCon and successive Synopsys User Groups, ensuring up-to-date VMM know-how, some of which can be accessed here >>.
Doulos VMM Training
- VMM Adopter Class
This 2-day class provides a quick-start, practical introduction to verification principles and in-depth practical application of VMM using Synopsys VCS™. Part of the Doulos SystemVerilog out of the Box™ program , it can be packaged and customized with components of Modular SystemVerilog, flexible project support options, and supplemental tool training in co-operation with Synopsys, to take delegates through to full SystemVerilog verification project readiness.
Class-based SystemVerilog verification is a critical part of the VMM learning curve. If it isn't taught well and understood, it undermines an engineer's ability to learn and apply VMM. Which is why, in the pre-requiste Comprehensive SystemVeilog training class, Doulos' careful handling of what many consider to be a challenging topic is key to the success of many clients. More >>
- Comprehensive SystemVerilog
This is a one-stop solution addressing the needs of both design and verification groups. It includes objective and up-to-date commentary on the two best-known published verification methodology approaches, and teaches key SystemVerilog language features that support them. More >>
- Modular SystemVerilog
Modular SystemVerilog consists of several modules that can be combined and customized into an integrated program to fulfil team-based training requirements. It includes:
- Fast-track Verilog for VHDL Users
- Fundamentals of SystemVerilog for Design
- Fundamentals of SystemVerilog for Verification
- SystemVerilog Assertions
- Module-based SystemVerilog Verification
- Class-based SystemVerilog Verification
- Verification Methodology Adopter Classes
Doulos Project Services is a powerful resource giving your company rapid access to expertise for direct use on project issues. A wide range of packages exist to assist you through all stages of methodology and language decision making, integration and design use. All our packages can be provided with the flexibility to provide support exactly when required, maximising the benefit to cost ratio.