Sunday 25 June 2017

Developing & Delivering KnowHow

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Online Training Events

Doulos is delighted to provide the following online training
webinars including live interactive Q&A. Registration and
attendence is FREE!

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View available Doulos On-Demand webinars »

Doulos Webinars



June 2017



Webinar:
Date:
Duration:
Presenter:
Getting Started with Yocto »
Wednesday June 21, 2017
1 hour session (all time zones covered)
Adrian Thomasset,
Senior Member Technical Staff
Yocto Project logo
Summary:
We will investigate how a minimal Linux system can be extended to include custom packaged software and demonstrate how standard Linux tools can be used in a stand-alone SDK. Key concepts of the Yocto Project build system, such as recipes, tasks and layers, will be introduced.

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Webinar:

Date:
Duration:
Presenter:
Maximize Design Productivity using Vivado
with SystemVerilog »

Friday June 23, 2017
1 hour session (all time zones covered)
Mike Smith
, Specialist Xilinx Trainer
SystemVerilog out of the box

Summary:
We will explore the features of SystemVerilog that are useful for RTL synthesis using the Xilinx Vivado Design Suite, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

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July 2017



Webinar:

Date:
Duration:
Presenter:
Software-based Design Flow to Accelerate
Programmable SoC devices »

Friday July 7, 2017
1 hour session (all time zones covered)
David C Black
, Doulos Senior Member Technical Staff
Xilinx SDSoC Logo

Summary:
We will explain how to use a Software-based design flow that will enable you to create custom hardware accelerators for extracting the optimum performance needed for your application requirements from All Programmable™ SoC and MPSoC devices.

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Webinars On-Demand




Doulos is pleased to now provide some of the webinars that have been previously broadcast On-Demand.

Verification
Advanced VHDL Verification - OS-VVM and more... »
How to take advantage of UVM-style run-time configuration in VHDL »
Webinars On-Demand

SystemVerilog Out of the Box
Synthesis-Friendly SystemVerilog »

Easier UVM
UVM: Now or Never? »
First Steps with UVM » Recording available in English, French and German
First Steps with UVM: Writing Tests »

Embedded Systems and ARM
NEW ARM V7-M Primer »
Squeezing the most out of battery-life using ARM Cortex-M processors »
CMSIS Turns 3.0 »
ARM Cortex-A9 MPCore »
ARM Cortex-A9 in the Altera SoC FGPA »

View all available Doulos on-demand webinars now »

 


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