Xilinx - How to Design a High-Speed Memory InterfaceView dates and locations
This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs.
Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.
The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex®-7 FPGA KC705 board.
Who Should Attend?
- VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
- Familiarity with logic design: state machines and synchronous design
- Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
- Familiarity with I/O basics and high-speed I/O standrd is also nice to have
- Vivado System Edition 2013.2
- Mentor HyperLynx SI
- Architecture: 7 series FPGAs*
- Demo board: Kintex-7 FPGA KC705 board*
- Identify the FPGA resources required for memory interfaces
- Describe different types of memories
- Utilize the Xilinx tools to generate memory interface designs
- Simulate memory interfaces with the Xilinx ISim simulator
- Implement memory interfaces
- Identify the board design options for the realization of memory interfaces
- Describe PCB-level simulation
- Test and debug your memory interface design
- Spartan-6 and Virtex-6 Family Overview
- Memory Devices
- Spartan-6 FPGA Memory Interfaces
- Virtex-6 FPGA Memory Interfaces
- MIG Design Generation
- Lab 1: MIG Core Generation
- MIG Design Simulation
- Lab 2: MIG Design Simulation
- MIG Design Implementation
- Lab 3: MIG Design Implementation
- Memory Interface Board-Level Design
- Memory Interface PCB Simulation
- Lab 4: Signal Integrity Simulation
- Memory Interface Test and Debugging
- Lab 6: MIG Design Debugging
- Lab 1: MIG Core Generation – Create a DDR2 or DDR3 memory controller using the Memory Interface Generator (MIG) CORE Generato™ interface. For Spartan-6 devices, customize the hard Memory Controller Block (MCB) targeting the SP601 or SP605 board. For Virtex-6 devices, customize the soft core memory controller for the ML605 board.
- Lab 2: MIG Design Simulation – Simulate the memory controller created in Lab 1 using ISim.
- Lab 3: MIG Design Implementation – Implement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality.
- Lab 4: Signal Integrity Simulation – Evaluate and perform basic verification options available for IBIS simulation of memory interfaces.
- Lab 5: MIG Design Debugging – Debug the memory interface design utilizing the ChipScope Pro™ tool.
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