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F2F TrainingSDSoC logoSDSoC Adopter Class

Combines Vivado HLS and Embedded C/C++ SDSoC Development Environment & Methodology
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SPECIAL OFFER: Delegates who attend the SDSoC Workshop day of this training class will receive a complimentary voucher to download the Xilinx SDSoC Development Kit worth $995.
Please contact the Doulos team for details.

Course Description

This 3 day combination training course provides the project-ready skills necessary to exploit the SDSoC Development Environment to create accelerated systems.

It combines training on Vivado HLS with a practical workshop using the SDSoC environment itself.

Full details of the two constituent training modules can be viewed using these links:

Training Duration

3 day

Who Should Attend?

Anyone interested in quickly adding hardware acceleration to a software system.

Prerequisites

  • Understanding of Zynq®-7000 architecture (with emphasis on ACP, HP ports, and internal routing)
  • Comfort with the C programming language

Software Tools

  • SDSoC development environment 2015.2

Hardware

  • Architecture: Zynq-7000 All Programmable SoC*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC. Check with Doulos for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Enhance productivity using Vivado HLS (high-level synthesis)
  • Describe the high-level synthesis flow
  • Use Vivado HLS for a first project
  • Identify the importance of the testbench
  • Use directives to improve performance and area and select RTL interfaces
  • Identify common coding pitfalls as well as methods for improving code for RTL/hardware
  • Perform system-level integration of blocks generated by Vivado HLS
  • Identify candidate functions for hardware acceleration by using the TCF profiling tool
  • Use the System Debugger's capabilities to control the execution flow and examine memory and variables during a debug session
  • Move designated software functions to hardware and estimate the performance of the accelerator and the effect on the entire system
  • Override tool defaults to improve the performance of the individual accelerators and the overall system

Course Outline

Day1
  • Introduction to High-Level Synthesis and Vivado HLS
  • Using Vivado HLS: GUI Flow
  • Lab 1: Introduction to the Vivado HLS Tool Flow
  • Vivado HLS Command Line Interface
  • Lab 2 Introduction to the Vivado HLS CLI Flow
  • Optimizing for Latency
  • Lab 3: The Impact of Unrolling Loops
Day 2
  • Optimizing for Throughput
  • Lab 4: Optimizing for Throughput
  • Optimizing Arrays
  • Lab 5: Handling Memories
  • Optimizing for Area
  • I/O Interfaces
  • Lab 6: Embedded System Integration
  • Vivado HLS: C Code
  • Lab 7: Matrix Multiplication
Day 3 (SDSoC Workshop)
  • Course Introduction
  • Zynq AP SoC Architecture Support for Accelerators [Optional]
  • Software Overview [Optional]
  • SDSoC Tool Overview {Lecture, Demos, Lab}
  • SDSoC Design Best Practices {Lecture, Demo}
  • Profiling {Lecture, Demo, Lab}
  • Debugging {Lecture, Demo, Lab}
  • Understanding Estimations {Lecture, Demo, Lab}
  • Blocking vs. Non-Blocking Implementations {Lecture, Lab}
  • Multiple Accelerators {Lecture, Lab}

    Delegates who attend Day 3 of this training will receive a complimentary voucher
    to download the Xilinx SDSoC Development Kit worth $995.



    Course Dates:
    June 18th, 2018 Ringwood, UK Enquire
    July 30th, 2018 San Jose, CA Enquire
    September 24th, 2018 Stockholm, SE Enquire
    September 24th, 2018 Copenhagen, DK Enquire
    October 10th, 2018 Ringwood, UK Enquire
    December 3rd, 2018 San Jose, CA Enquire
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    Looking for team-based training, or other locations?

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