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F2F TrainingSDSoC logoSDSoC Workshop

Also known as Embedded C/C++ SDSoC
Development Environment and Methodolog
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SPECIAL OFFER: Delegates who attend this training class will receive a complimentary voucher to download the Xilinx SDSoC Development Kit worth $995. Contact the Doulos team for details.

Course Description

This one-day course is structured to help designers new to the SDSoC™ development environment to quickly create accelerated systems. The focus is on utilizing the tools to accelerate an existing design at the system architecture level, not on the optimization of the accelerator microarchitectures.

Several optional modules are provided to quickly provide students with the necessary background on both hardware and software.

Do you need High Level Synthesis training? Check out the SDSoC Adopter Class which incorporates this training

Training Duration

1 day

Who Should Attend?

Anyone interested in quickly adding hardware acceleration to a software system.


  • Understanding of Zynq®-7000 architecture (with emphasis on ACP, HP ports, and internal routing)
  • Comfort with the C programming language
  • Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK

High Level Synthesis training is included in the SDSoC Adopter Class.

Software Tools

  • SDSoC development environment 2015.2


  • Architecture: Zynq-7000 SoC*
  • Demo board: Zynq-7000 SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 SoC. Check with Doulos for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify candidate functions for hardware acceleration by using the TCF profiling tool
  • Use the System Debugger's capabilities to control the execution flow and examine memory and variables during a debug session
  • Move designated software functions to hardware and estimate the performance of the accelerator and the effect on the entire system
  • Override tool defaults to improve the performance of the individual accelerators and the overall system

Course Outline

  • Course Introduction
  • Zynq AP SoC Architecture Support for Accelerators [Optional]
  • Software Overview [Optional]
  • SDSoC Tool Overview {Lecture, Demos, Lab}
  • SDSoC Design Best Practices {Lecture, Demo}
  • Profiling {Lecture, Demo, Lab}
  • Debugging {Lecture, Demo, Lab}
  • Understanding Estimations {Lecture, Demo, Lab}
  • Blocking vs. Non-Blocking Implementations {Lecture, Lab}
  • Multiple Accelerators {Lecture, Lab}

Topic Descriptions

  • Zynq AP SoC Architecture Support for Accelerators [Optional] - Discusses the relevant aspects of the Zynq SoC architecture for accelerator design. The focus is on AXI ports and protocols, system latency, and memory utilization.
  • Software Overview [Optional] - Provides a thorough understanding of how the integrated design environment works, including how the compiler and linker behave, basics of makefiles, DMA usage, and variable scope.
  • SDSoC Tool Overview {Lecture, Demos, Lab} - Introduces the purpose, underlying structures, and basic functionality of the SDSoC development environment through a combination of lecture and demonstration. Student will cement their knowledge with a lab that reinforces the concepts provided in the lecture and demo.
  • SDSoC Design Best Practices {Lecture, Demo} - Illustrates common mistakes and how to avoid them. Also describes approaches to refactoring software for hardware acceleration.
  • Profiling {Lecture, Demo, Lab} - Profiling is the process that identifies how the processor is spending its time. Through profiling, the user can quickly identify which functions must be optimized or moved to hardware to satisfy the performance requirements.
  • Debugging {Lecture, Demo, Lab} - Through the use of the System Debugger, students will learn how to follow the control flow in an executing application and see the effects of the code on memory to successfully debug software issues.
  • Understanding Estimations {Lecture, Demo, Lab} - Once a function is moved to hardware, questions remain: Will the accelerator fit in hardware? Will it fun fast enough? Estimations can provide the answers.
  • Blocking vs. Non-Blocking Implementations {Lecture, Lab} - Addresses how the processor behaves while the accelerator is producing solutions - does it wait or continue on?
  • Multiple Accelerators {Lecture, Lab} - There are times when moving a single function to hardware is not enough - multiple functions must be moved to hardware, or one accelerator must be duplicated. Here students will learn to control how the tool produces the accelerators.

Course Dates:
November 20th, 2020 Ringwood, UK Enquire
indicates CONFIRMED TO RUN courses.

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