Wednesday 15 August 2018

Developing & Delivering KnowHow

Home > Training > Zynq UltraScale+ MPSoC for the Hardware Designer

F2F TrainingZynq UltraScale+ MPSoC for the Hardware Designer

View workshop dates and locations

Course Description

This one-day course is structured to provide hardware designers with an overview of many of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.

Training Duration

1 day

Who Should Attend?

Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.

Prerequisites

  • Suggested: Understanding of the Zynq-7000 architecture
  • Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

Software Tools

  • Vivado® Design Suite 2016.3
    • May require special Zynq UltraScale+ MPSoC family license
  • Hardware emulation environment:
    • VirtualBox
    • QEMU
    • Ubuntu desktop
    • PetaLinux

Hardware

  • Host computer for running the above software*

* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with Doulos for the specifics of the in-class lab environment or other customizations. The 2015.4 version of this class does not use a physical board, but rather a local emulation environment and the Vivado Design Suite.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • List the various power domains and how they are controlled
  • Describe the connectivity between the processing system (PS) and programmable logic (PL)
  • Utilize QEMU to emulate hardware behavior

Course Outline

  • 1.1 Zynq UltraScale+ MPSoC Application Processing Unit
    Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed.
    {lab / lecture}
  • 1.2 Zynq UltraScale+ MPSoC HW-SW Virtualization
    Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.
    {lab / lecture / demo}
  • 1.3 Zynq UltraScale+ MPSoC Real-Time Processing Unit
    Introduction to the various elements within the RPU and different modes of configuration.
    {lab / lecture / demo}
  • 1.4 QEMU
    Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.
    {lab / lecture}
  • 1.5 Zynq UltraScale+ MPSoC Booting
    How to implement the embedded system, including the boot process and boot image creation.
    {lab / lecture}
  • 1.6 Zynq UltraScale+ MPSoC System Protection
    Covers all the hardware elements that support the separation of software domains.
    {lab / lecture}
  • 1.7 Zynq UltraScale+ MPSoC Clocks and Resets
    Overview of clocking and reset, focusing more on capabilities than specific implementations.
    {lecture / demo}
  • 1.8 AXI
    Understanding how the PS and PL connect enables designers to create more efficient systems.
    {lab / lecture / demo}
  • 1.9 Zynq UltraScale+ MPSoC PMU
    Overview of the PMU and the power-saving features of the device.
    {lab / lecture}


Looking for team-based training, or other locations?

Complete an on-line form and a Doulos representative will get back to you »

Back to top
Privacy Policy Site Map Contact Us