Arm Cortex-A9 for Zynq System Design
Standard Level - 3 daysview dates and locations
This course covers both the system and software aspects of designing with an Arm® Cortex®-A9 MPCore based device, highlighting the core architecture details and the Xilinx® Zynq® implementation choices. Topics include the Arm exceptions' model, details of the available caching schemes and coherency management, memory management and the Arm memory model, as well as the AMBA AXI bus protocol. Additionally the Arm assembly section delivers the essential knowledge required for programing and debugging an Arm v7 based application processor.
The learning is reinforced with unique Lab exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
Engineers who wish to learn about other features and benefits of the Xilinx Zynq programmable SoC (aside from details of the Arm Cortex-A9 processing system) may wish to attend Zynq System Architecture, which covers the architecture of the processing system (PS) and the integration of programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize Zynq. (Zynq System Architecture covers the Cortex-A9 architecture in approximately 1 hour as opposed to 3 days.)
Who should attend?
- Engineers who wish to become skilled in the use of a Cortex-A9 based System On Chip from a software and verification perspective
- Engineers who need to understand integration details centered around the AXI protocol
- Engineers who will required to provide a software solution to bring a bare metal Cortex-A9 MPCore system to life.
What will you learn?
- The hardware structure of a Zynq device
- The details of a Cortex-A9 processor core
- The details of the MPCore logic
- Memory management for Arm v7 based devices
- AXI system interfaces
- Bringing up a bare metal system
Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.
C programming for Embedded Systems training is also available from Doulos.
A carefully crafted combination of content from Arm, Xilinx and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes:
- Fully indexed course notes creating a complete reference manual
Day 1, am
Introduction to Zynq
- Architecture details with Cortex-A9 MPCore implementation choices
- Core and FPGA interfaces
- Processing System Built-in Peripherals
- Memories and Memory Controllers
- FPGA logic and rooting details
- I/O Peripherals
- Processor System Boot Options
- Cortex-A9 core building blocks
- Private peripherals
- Snoop control unit
- Accelerator coherency Port (ACP)
- Generic interrupt controller
- Core system interfaces
Caches and Tightly Coupled Memories
- Cache basics
- Caches on Arm processors
- Tightly Coupled Memory (TCM)
- Optimization consideration
Day 1, pm
Introduction to Arm assembler programming (including Labs - see below)
- Load/Store Instructions
- Data Processing Instructions
- Flow Control
Day 2, am
Using the NEON co-processor
- NEON Instruction Set Overview
- NEON Software Support.
Exception Handlers for Arm application processors
- Exceptions overview
- Interrupts sources and priorities
- Abort Handlers
- SVC Handlers
- Undef Handlers
- Reset Handlers
Day 2, pm
- Memory Management Introduction
- Access Permissions and Types
- Memory Protection Unit (MPU)
- Memory Management Unit (MMU)
- Optimizations & Issues
- Synchronization primitives
- SWP Instruction
- LDREX / STREX and CLREX Instructions
Embedded software development
- An out-of-the-box” build
- Tailoring the C library to your target
- Tailoring image memory map to your target
- Reset and Initialization
- Further memory map considerations
- Building and debugging your image.
Day 3, am
Software Engineer's Guide to Zynq
- Zynq Peripherals
- Cortex-A9 Pipeline
- Media Processing Engine
- Register Renaming
- Fast Loop Mode
- Program Flow Prediction
- Preformance Monitoring Unit
- Level One Memory System
Day 3, pm
- MPCore Features
- Snoop Control Unit
- Accelerator Coherency Port (ACP)
- Interrupt Controller
- Timer and watchdog
- TrustZone Support
- Developing for Arm MPCore Processors
- Booting SMP
- Configuring an interrupt
The AMBA AXI bus protocol
- Channels, Transfers & Transactions
- Channel Signal
- Transfer Behavior
- Transaction Ordering
- AXI Terminology.
Introduction to TrustZone
- Exception Handling
- Memory System
Compiler Hints and Tips
- Basic Compilation
- Compiler Optimizations
- Coding Considerations
- Local and Global Data Issues
Linker and Libraries
- Linking Basics
- System and User Libraries
- Veneers and Interworking
- Linker Optimizations and Diagnostics
- Arm Supplied Libraries
The learning is reinforced with unique Lab Exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on the default development tool-set offered by Xilinx as well as a remote debug session based on a combination of GDB and the Zynq QEMU platform used for fast prototyping.
Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/CGDB and QEMU).
|March 30th, 2020||Ankara, TR||Enquire|
|June 17th, 2020||Ringwood, UK||Enquire|
|indicates CONFIRMED TO RUN courses.|
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