Standard Level - 5 sessionsview dates and locations
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content, and delivers similar learning outcomes, as a scheduled face-to face class.
This course covers both the system and software aspects of designing with an Arm® Cortex®-A9 MPCore based device, highlighting the core architecture details and the Xilinx® Zynq® programmable SoC implementation choices.
Topics include the Arm exceptions model, details of the available caching schemes and coherency management, memory management and the Arm memory model. Additionally the sections on the v7 architecture instruction set and steps involved in initializing an MPCore system deliver the essential knowledge required for programming and debugging a Cortex-A9 MPCore processor.
Hands-on LabsThe learning is reinforced with unique Lab exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
FormatThe format of Live ONLINE training from Doulos is focused on delivery of a single 4 hour intensive session per day. This includes live tuition and class interaction with the Doulos subject matter expert during the full scope of each session.
Labs are usually incorporated within the 4 hour sessions with the Doulos lab platform providing individual (private) tutor support at all times for each delegate. On occasion, labs may require time outside of the 4 hour session to complete. Additional lab material is available in some subjects for individuals to reinforce their understanding of the course content.
Associated learningEngineers who wish to learn about other features and benefits of the Xilinx Zynq programmable SoC (aside from details of the Arm Cortex-A9 processing system) may wish to attend Zynq System Architecture Online, which covers the architecture of the processing system (PS) and the integration of programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize Zynq.
This class is offered in the same Zynq Adopter ONLINE training program scheduled to run over two consecutive weeks
Who should attend?
- Engineers who wish to become skilled in the use of a Cortex-A9 based System On Chip from a software development and verification perspective.
- Engineers who will required to provide a software solution to bring a bare metal Cortex-A9 MPCore system to life.
- Engineers who need to implement an operating system running on an Arm v7 processor.
What will you learn?
- The hardware structure of a Zynq device
- The details of a Cortex-A9 processor core
- The details of the MPCore logic
- Memory management for Arm v7 based devices
- Bare metal system bring-up
Pre-requisitesDelegates should have some knowledge of embedded systems, and a basic understanding of embedded programming in C and assembler.
Knowledge of earlier Arm architectures is an advantage but not necessarily required.
The source training materials include novel content (presentation and labs) developed by Doulos supplementing approved training materials provided under license from Arm for Arm Cortex-A9 MPCore software design.
Session 1Introduction to Zynq
- Architecture details with Cortex-A9 MPCore implementation choices
- Core and FPGA interfaces
- Processing System Built-in Peripherals
- Memories and Memory Controllers
- FPGA logic and rooting details
- I/O Peripherals
- Processor System Boot Options
- Cortex-A9 core building blocks
- Private peripherals
- Snoop control unit
- Accelerator coherency Port (ACP)
- Generic interrupt controller
- Core system interfaces
Introduction to the Arm v7 instruction set architecture
- Arm v7 Unified Assembly Language
Hands-on Lab session
- Assembly Language Basics
- Assembly Language Data Processing
- Cache basics
- Caches on Arm processors
- Optimization consideration
Exception Handlers for Arm application processors
- Exceptions overview
- Interrupts sources and priorities
- Abort Handlers
- SVC Handlers
- Undef Handlers
- Reset Handlers
Hands-on Lab session
- Exceptions Handling
- Peripherals Driver Design
Session 3Memory Management
- Memory Management Introduction
- Access Permissions and Types
- Memory Protection Unit (MPU)
- Memory Management Unit (MMU)
- Optimizations & Issues
Using the NEON co-processor
- NEON Instruction Set Overview
- NEON Software Support
Writting C for Arm
- Parameter Passing
- Floating Point Linkage
- Coding Considerations
Session 4Synchronization Support
- Synchronization primitives
- SWP Instruction
- LDREX / STREX and CLREX Instructions
Embedded software development
- An out-of-the-box” build
- Tailoring the C library to your target
- Tailoring image memory map to your target
- Reset and Initialization
- Further memory map considerations
- Building and debugging your image
Software Engineer's Guide to Zynq
- Zynq Peripherals
- Cortex-A9 Pipeline
- Media Processing Engine
- Register Renaming
- Fast Loop Mode
- Program Flow Prediction
- Preformance Monitoring Unit
- Level One Memory System
Session 5MPCore Logic
- MPCore Features
- Snoop Control Unit
- Accelerator Coherency Port (ACP)
- Interrupt Controller
- Timer and watchdog
- TrustZone Support
- Developing for Arm MPCore Processors
- Booting SMP
- Configuring an interrupt
- Exception Handling
- Memory System
- Software Implementation
The learning is reinforced with unique Lab Exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on the default development tool-set offered by Xilinx as well as a remote debug session based on a combination of GDB and the Zynq QEMU platform used for fast prototyping.
Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/CGDB and QEMU).
|June 3rd, 2019||ONLINE EurAsia||Enquire|
|November 18th, 2019||ONLINE Americas||Enquire|
|December 2nd, 2019||ONLINE EurAsia||Enquire|
|indicates CONFIRMED TO RUN courses.|
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