Monday 25 September 2017

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Xilinx - Embedded Systems Hardware and Software Design

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PLEASE NOTE BEFORE YOU BOOK ON THIS COURSE:
Xilinx is migrating from the use of the ISE Design Suite (including Xilinx Platform Studio) to the new Vivado Design Suite which includes the IP Integrator environment. It is important to consider your particular tool requirements and discuss them with your local Doulos representative before making arrangements to attend this course.


This course brings experienced FPGA designers up to speed on developing embedded systems for the Zynq All Programmable SoC. The basic features and capabilities of Zynq are also included in the lectures and labs. These hands-on labs are plentiful and provide personal experience with the development, debugging and simulation of an embedded system.

Additionally, the features and capabilities of the Xilinx MicroBlaze™ soft processor are also included in the lectures.

This course uses materials developed by Xilinx and conveniently combines the courses:


Training Duration

3 days

Who should attend?

Software and hardware design engineers who are interested in developing embedded systems with the Xilinx Zynq All Programmable SoC. (Looking to develop with Microblaze? Click here ».)

Pre-requisites

  • FPGA design experience
  • Completion of Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE® software implementation tools
  • Basic understanding of C or C++ programming (including general debugging techniques)
  • Some HDL modelling experience
  • Conceptual understanding of embedded processing systems including device drivers, interrupt routines writing / modifying scripts, user applications and boot loader operation

Software Tools

  • Vivado® Design or System Edition 2014.1

Hardware

  • Architecture: Zynq® All Programmable SoC and 7 series FPGAs*
  • Demo board: Zed

* This course focuses on the Zynq All Programmable SoC and 7 Series FPGA architectures. Please contact Doulos for the specifics of the in-class lab board, other customizations or architecture.

Developing for 6 Series FPGAs?

You can also attend this course if you intend to use the Xilinx MicroBlaze soft processor in a 6 Series FPGA such as Spartan-6 or Virtex-6. Please contact Doulos for the specifics of your requirements before booking.

Skills gained

After completing this training, you will be able to:
  • Describe the various tools that encompass a Xilinx embedded design
  • Rapidly architect an embedded system containing a Cortex®-A9 processor by using the Vivado IP Integrator and PS Configuration Wizard
  • Create and integrate a processing system component
  • Design and add a custom peripheral
  • Bus Functional Model Simulation
  • Implement an effective software design environment for a Xilinx embedded system using the Xilinx SDK tools
  • Write a basic user application using the Xilinx Software Development Kit (SDK) and run it on the embedded system
  • Use Xilinx debugger tools to troubleshoot user applications

Associated Courses

Course Outline

Day 1

  • EDK Overview
  • IP Integrator and the Processing System Configuration Wizard
  • Lab 1: Hardware Construction with the Vivado IP Integrator Tool
  • Software Development Using SDK
  • Lab 2: Adding and Downloading Software
  • Introduction to AXI
  • Interrupts
  • Adding Hardware to an Embedded Design
  • Lab 3: Adding IP to a Hardware Design

Day 2

  • MicroBlaze Processor Basics (optional)
  • Cortex-A9 Processor Basics
  • Designing a Custom Peripheral
  • Adding Custom IP to the Embedded System
  • Bus Functional Model Simulation
  • Lab 4: Sharing PS Resources with the MicroBlaze Processor Ė Hardware

Day 3

  • Software Platform Development
  • Lab 5: Basic System Implementation
  • Software Development Using SDK
  • Writing Code in the Standalone Xilinx Environment
  • Lab 6: Application Development
  • Address Management
  • Application Debugging
  • Lab 7: Debugging

Lab Descriptions

  • Lab 1: Hardware Construction using the Vivado IP Integrator Tool (Zynq All Programmable SoC) – Create a project using the IP Integrator to develop a basic hardware system and generate a series of netlists for the embedded design.
  • Lab 2: Adding and Downloading Software – Complete the processes begun in Lab 1 using the SDK tools to create a software BSP and sample application. Configure the device and download the application.
  • Lab 3: Adding IP to a Hardware Design – Add IP to an existing processing system. Configure the device and download the application.
  • Lab 4: Sharing PS Resources with the MicroBlaze Processor – Hardware –Sharing PS Resources with the MicroBlaze Processor (Hardware) – Add peripherals to a Zynq All Programmable SoC design and connect the PS to a PL processor (i.e., a MicroBlaze processor to share PS resources). Generate the netlists and bitstream of the complete design.
  • Lab 5: Basic System Implementation – Construct the hardware and software platforms used for the course labs. Begin with Processing System Configuration Wizard (Zynq All Programmable SoC) to create the hardware design. Specify a basic software platform and add a software application to the system.
  • Lab 6: Application Development – Create a simple software application project with the provided source files for a software loop-based stopwatch. Verify proper BSP settings and linker script generation. Use API documentation for the GPIO peripheral to complete the software application. Verify proper operation of the stopwatch in hardware.
  • Lab 7: Debugging – Launch the SDK debug perspective and the previous labís stopwatch application for debugging, setting breakpoints, calculating interrupt latency, and stepping through the programís operation.

Course Dates:
October 31st, 2017 Ringwood, UK Enquire
indicates CONFIRMED TO RUN courses.

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