Xilinx Partial ReconfigurationView dates and locations
Who should attend?
- Architecture: UltraScale and 7 series FPGAs*
- Demo board: Kintex® UltraScale FPGA KCU105 board, Kintex-7 FPGA KC705 board, and ZedBoard
* This course focuses on the UltraScale and 7 series architectures. Check with Doulos for the specifics of the in-class lab board or other customizations.
** The UltraScale architecture versions of the "Using the PRC IP in a Partial Reconfiguration Design" lab and the "Using ILA Cores to Debug Partial Reconfiguration Designs" lab are not available because of QSPI and PRC issues on the KCU105 board. These two labs support only the 7 series architecture. The "Partial Reconfiguration in Embedded Systems" lab requires a ZedBoard for implementation.
- Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
- Define PR regions and reconfigurable modules with the Vivado Design Suite
- Generate the appropriate full and partial bitstreams for a PR Design
- Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs
- Implement a Partial Reconfiguration systemusing the following techniques:
- Direct JTAG connection
- Timing constraints and analysis
- Partial Reconfiguration Methodology
- Demo: Partial Reconfiguration Flow
- Partial Reconfiguration Tool Flow
- Lab 1: Partial Reconfiguration Flow
- Partial Reconfiguration Design Recommendations
- Lab 2: Floorplanning
- Optional: FPGA Configuration Overview
- Partial Reconfiguration Bitstreams
- Demo: Partial Reconfiguration Controller (PRC) IP
- Lab 3: Using the PRC IP in Partial Reconfiguration Designs
- Managing Clocks, I/Os, and GTs
- Managing Timing
- Lab 4: Partial Reconfiguration Timing Analysis and Constraints
- Partial Reconfiguration in Embedded Systems
- Lab 5: Partial Reconfiguration in Embedded Systems
- Debugging Partial Reconfiguration Designs
- Lab 6: Using ILA Cores to Debug Partial Reconfiguration Designs
- Lab 1: Partial Reconfiguration Flow – Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
- Lab 2: Floorplanning – Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock.
- Lab 3: Using the PRC IP in Partial Reconfiguration Designs – Illustrates using the PRC IP and hardware triggers to manage partial bitstreams.
- Lab 4: Partial Reconfiguration Timing Analysis and Constraints – Shows how area groups and Reconfigurable Partitions affect design performance.
- Lab 5: Partial Reconfiguration in Embedded Systems – Illustrates implementing PR designs in an embedded environment.
- Lab 6: Using ILA Cores to Debug Partial Reconfiguration Designs – Demonstrates using ILA cores to debug PR designs and shows which signals to monitor during debugging.
Looking for team-based training, or other locations?
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