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Doulos Live Online trainingXilinx Partial Reconfiguration Tools & Techniques ONLINE

Standard Level - 4 sessions

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PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.

It covers the same scope and content as a scheduled face-to face class and delivers comparable learning outcomes. Daily sessions comprise 4-6 hours of class contact time.

Course Description

Learn how to construct, implement, and download a Partially Reconfigurable (PR) FPGA design using the Vivado® Design Suite. This course covers both the tool flow and mechanics of successfully creating a PR design.
The emphasis is on:
  • Identifying best design practices and understanding the subtleties of the PR design flow
  • Using the PR controller and PR decoupler IP in the PR process
  • Implementing PR in an embedded system environment
  • Applying appropriate debugging techniques on PR designs
  • Employing best practice coding styles for a PR system.

Who should attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who have need of partial reconfiguration techniques.


Software Tools

Vivado Design or System Edition (latest version). Please check your specific requirements with Doulos.

Hardware Tools

Architecture: UltraScale and 7 series FPGAs (This course focuses on the UltraScale and 7 series architectures)

No board supplied. Labs are demonstrated by the instructor.

Skills Gained

After completing this comprehensive training, you will know how to:
  • Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
  • Define PR regions and reconfigurable modules with the Vivado Design Suite
  • Generate the appropriate full and partial bitstreams for a PR design
  • Use the Internal Configuration Access Port (ICAP) and Processor Configuration Access Port (PCAP) components to deliver the partially reconfigurable systems
  • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers and MGTs
  • Implement a Partial Reconfiguration system using the following techniques:
    • Direct JTAG connection
    • Floorplanning
    • Timing constraints and analysis
  • Implement a PR system using the Partial Reconfiguration Controller (PRC) IP
  • Implement a PR system in an embedded environment
  • Debug PR designs

Course Outline

Sessions 1 & 2

  • Introduction to Partial Reconfiguration
  • Demo: Introduction to Partial Reconfiguration
  • Partial Reconfiguration Flow
  • Lab 1: Partial Reconfiguration Tool Flow
    Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will be able to download a partial bitstream to the KCU105 (UltraScale) board via the JTAG connection.
  • Lab 2: Partial Reconfiguration Project Flow
    Illustrates Partial Reconfiguration (PR) project flow in the Vivado Design Suite. At the end of this lab, you will be able to create multiple RMs and configurations using Partial Reconfiguration Wizard.
  • Lab 3: Floorplanning the PR Design
    Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock. Partial Reconfiguration Design Considerations
  • Optional: FPGA Configuration Overview
  • Partial Reconfiguration Bitstreams
  • Demo: Partial Reconfiguration Controller (PRC) IP
  • Lab 4: Using the Partial Reconfiguration Controller in a PR Design
    Illustrates using the PRC IP and hardware triggers to manage partial bitstreams.

Sessions 3 & 4

  • Partial Reconfiguration: Managing Timing
  • Lab 5: Partial Reconfiguration Timing Analysis and Constraints
    Shows how area groups and Reconfigurable Partitions affect design performance.
  • Partial Reconfiguration in Embedded Systems
  • Lab 6: Partial Reconfiguration in Embedded Systems
    The course instructor will demonstrate implementing PR designs in an embedded environment.
  • Debugging Partial Reconfiguration Designs
  • PR Debug Demonstration: The instructor will demonstrate debugging a Partial Reconfiguration Design using Integrated Logic Analyzer (ILA) cores to debug PR designs and shows which signals to monitor during debugging.
  • Partial Reconfiguration Design Recommendations
  • PCIe Core and Partial Reconfiguration


Course Dates:
August 24th, 2020 ONLINE EurAsia Enquire
September 28th, 2020 ONLINE Americas Enquire
November 9th, 2020 ONLINE EurAsia Enquire
November 30th, 2020 ONLINE Americas Enquire
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