• Identifying best design practices and understanding the subtleties of the PR design flow
• Using the PR controller and PR decoupler IP in the PR process
• Implementing PR in an embedded system environment
• Applying appropriate debugging techniques on PR designs
• Employing best practice coding styles for a PR system.

• Vivado FPGA Essentials
• Vivado Advanced XDC and STA
• Vivado Advanced Tools and Techniques
• Working HDL knowledge (VHDL or Verilog knowledge)

Architecture: UltraScale and 7 series FPGAs (This course focuses on the UltraScale and 7 series architectures)

No board supplied. Labs are demonstrated by the instructor.

• Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
• Define PR regions and reconfigurable modules with the Vivado Design Suite
• Generate the appropriate full and partial bitstreams for a PR design
• Use the Internal Configuration Access Port (ICAP) and Processor Configuration Access Port (PCAP) components to deliver the partially reconfigurable systems
• Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers and MGTs
• Implement a Partial Reconfiguration system using the following techniques:
• Direct JTAG connection
• Floorplanning
• Timing constraints and analysis
• Implement a PR system using the Partial Reconfiguration Controller (PRC) IP
• Implement a PR system in an embedded environment
• Debug PR designs

• Introduction to Partial Reconfiguration
• Demo: Introduction to Partial Reconfiguration
• Partial Reconfiguration Flow
• Lab 1: Partial Reconfiguration Tool Flow
  Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will be able to download a partial bitstream to the KCU105 (UltraScale) board via the JTAG connection.
• Lab 2: Partial Reconfiguration Project Flow
  Illustrates Partial Reconfiguration (PR) project flow in the Vivado Design Suite. At the end of this lab, you will be able to create multiple RMs and configurations using Partial Reconfiguration Wizard.
• Lab 3: Floorplanning the PR Design
  Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock. Partial Reconfiguration Design Considerations
• Optional: FPGA Configuration Overview
• Partial Reconfiguration Bitstreams
• Demo: Partial Reconfiguration Controller (PRC) IP
• Lab 4: Using the Partial Reconfiguration Controller in a PR Design
  Illustrates using the PRC IP and hardware triggers to manage partial bitstreams.

• Partial Reconfiguration: Managing Timing
• Lab 5: Partial Reconfiguration Timing Analysis and Constraints
  Shows how area groups and Reconfigurable Partitions affect design performance.
• Partial Reconfiguration in Embedded Systems
• Lab 6: Partial Reconfiguration in Embedded Systems
  The course instructor will demonstrate implementing PR designs in an embedded environment.
• Debugging Partial Reconfiguration Designs
• PR Debug Demonstration: The instructor will demonstrate debugging a Partial Reconfiguration Design using Integrated Logic Analyzer (ILA) cores to debug PR designs and shows which signals to monitor during debugging.
• Partial Reconfiguration Design Recommendations
• PCIe Core and Partial Reconfiguration