Xilinx - Vivado Advanced XDC and STA ONLINEincluding UltraFast Design Methodology *
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Summary course description:
In this training you will learn about the underlying database and Static Timing Analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx Design Constraints (XDC) and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
In addition you will learn about:
- making path-specific, false path, and min/max timing constraints, as well as timing constraint priority in the Vivado timing engine.
- the scripting environment of the Vivado Design Suite and how to use the project-based and non-project batch scripting flows.
- sophisticated aspects of the Vivado Design Suite, enabling you to use its advanced capabilities to achieve design closure.
- the UltraFast™ Design Methodology, which encapsulates the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. The UltraFast design methodology checklist is also introduced.
* This training by Doulos is based on materials provided by Xilinx from the following courses :
- Vivado Advanced XDC and Static Timing Analysis for ISE Software Users
- and UltraFast™ Design Methodology
Who Should Attend?
FPGA designers looking to utilize Vivado who:
- currently use the Xilinx ISE® Design Suite
- already have some familiarity with Xilinx 7-Series devices
PLEASE NOTE: Engineers who are unfamiliar with Xilinx devices with no prior Xilinx ISE Design Suite experience should attend Vivado Adopter Class for New Users. This course provides new users with a good grounding immediately prior to this more advanced training. Find out more using the link above or contact Doulos for further information.
Engineers wishing to design with 6-series devices should contact Doulos for further information.
- Basic knowledge of the VHDL or Verilog language
- Digital design knowledge
- Completion of Vivado Design Suite Online, is strongly recommended - or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture, and FPGA design techniques.
Recommended additional training
- Essential Tcl for Vivado (online) teaches the essentials of the Tcl language with particular focus on its application within the Xilinx Vivado™ Design Suite*. It can be taken independently either before or after Vivado Adopter training as convenient (subject to availability).
- It is strongly recommended that you take this training as part of Doulos' Vivado Adopter Class for New Users Online or Vivado Adopter Class Online (depending on your previous experience) in which you will also learn about the Vivado Design Suite and other essential background about designing with Xilinx FPGAs.
- Vivado System Edition 2017.3
After completing this comprehensive training, you will have the necessary skills to:
- Apply clock and I/O timing constraints and perform timing analysis
- Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
- Describe and use the clock resources in a design
- Generate a DRC report to detect and fix design issues early in the flow
- Describe the "baselining" process to gain timing closure on a design
- Apply baseline constraints to determine if internal timing paths meet design timing objectives
- Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
- Analyze a timing report to identify how to center the clock in the data eye
- Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
- Define a properly constrained design
- Increase performance by utilizing FPGA design techniques
- Utilize floorplanning techniques to improve design performance
- Employ advanced implementation options, such as incremental compile flow and physical optimization techniques
- Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
- Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
- Build resets into your system for optimum reliability and design speed
- Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle.
- I/O Constraints and Virtual Clocks
Apply I/O constraints and perform timing analysis
- Timing Summary Report
Use the post-implementation timing summary report to sign-off criteria for timing closure
- Generated Clocks
Use the report clock networks report to determine if there are any generated clocks in a design
- Clock Group Constraints
Apply clock group constraints for asynchronous clock domains
- Introduction to Timing Exceptions
Introduces timing exception constraints and applying them to fine tune design timing
- Synchronization Circuits
Use synchronization circuits for clock domain crossings
- Report Clock Interaction
Use the clock interaction report to identify interactions between clock domains
- Timing Constraints Priority
Identify the priority of timing constraints
- Case Analysis
Understand how to analyze timing when using multiplexed clocks in a design
- Revision Control Systems in the Vivado Design Suite
Use version control systems with Vivado design flows.
- UltraFast Design Methodology: Planning
Introduces the methodology guidelines on planning and the UltraFast Design Methodology checklist
- UltraFast Design Methodology: Design Creation and Analysis
Overview of the methodology guidelines covered in this course.
- HDL Coding Techniques
Covers basic digital coding guidelines used in an FPGA design
Investigates the impact of using asynchronous resets in a design
Use Xilinx-recommended baselining procedures to progressively meet timing closure
- I/O Timing Scenarios
Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data
- System-Synchronous I/O Timing
Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface
- Source-Synchronous I/O Timing
Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface
- Report Datasheet
Use the datasheet report to find the optimal setup and hold margin for an I/O interface
- UltraFast Design Methodology: Design Closure
Introduces the UltraFast design methodology guidelines on design closure
- UltraFast Design Methodology: Advanced Techniques
Introduces the methodology guidelines for advanced techniques
- Introduction to Floorplanning
Introduction to floorplanning and how to use Pblocks while floorplanning
- Physical Optimization
Use physical optimization techniques for timing closure
Optional TopicsThe following topics are included in the course materials and, if time permits, may be covered during the course at the instructor’s discretion and according to the delegates’ interest.
- Timing Simulation
Simulate the design post-implementation to verify that a design works properly on hardware.
- Creating and Packaging Custom IP
Create your own IP and package and include it in the Vivado IP catalog.
- Introduction to the Xilinx Tcl Store
Introduces the Xilinx Tcl Store.
Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
- Design Analysis and Floorplanning
Explore the pre- and post-implementation design analysis features of the Vivado IDE.
- Vivado Design Suite ECO Flow
Use ECO flow to make changes to a previously implemented design and apply changes to the original design.
- Bitstream Security
Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication.
|December 16th, 2019||ONLINE Americas||Please call|
|March 16th, 2020||ONLINE EurAsia||Enquire|
|March 16th, 2020||ONLINE Americas||Enquire|
|June 15th, 2020||ONLINE Americas||Enquire|
|June 29th, 2020||ONLINE EurAsia||Enquire|
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