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Doulos Face-to-Face TrainingXilinx - UltraFast Design Methodology

Previously known as Vivado Design Methodology for
ISE Software Project Navigator Users
by Xilinx.

The content of this course module is included within the Vivado Adopter Class course (shown below) and Vivado Adopter Class for New Users.

Doulos Face-to-Face TrainingXilinx - Vivado Adopter Class for New Users

This course comprises:
Vivado Design Suite, Vivado Advanced XDC & STA
and UltraFast Design Methodology
*
with an additional introductory day on essential FPGA design
view dates and locations

Vivado LogoTraining Duration

5 days

Course Description

Day 1 is specifically designed for designers who are new to Xilinx devices. This day will enable you to:

  • build an effective FPGA design using synchronous design techniques
  • understand the configuration process
  • instantiate appropriate device resources
  • use proper HDL coding techniques

Days 2 and 3 provide introductory training on the Vivado Design Suite. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.

In days 4 and 5, learn the underlying database and Static Timing Analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx Design Constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.

You will also learn about:

  • making path-specific, false path, and min/max timing constraints, as well as timing constraint priority in the Vivado timing engine.
  • the scripting environment of the Vivado Design Suite and how to use the project-based and non-project batch scripting flows.
  • sophisticated aspects of the Vivado Design Suite, enabling you to use its advanced capabilities to achieve design closure.
  • the UltraFastâ„¢ Design Methodology, which encapsulates the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. The UltraFast design methodology checklist is also introduced.

* This training by Doulos is based on materials provided by Xilinx® from the following courses :
  • Vivado® Design Suite for ISE Software Project Navigator Users
  • Vivado® Advanced XDC and Static Timing Analysis for ISE Software Users
  • and UltraFast™ Design Methodology

Who Should Attend?

  • Digital designers who have a working knowledge of an HDL (VHDL, Verilog or SystemVerilog) but are new to Xilinx FPGAs.
  • Existing Xilinx ISE users who have little or no knowledge of 7-Series or UltraScale devices.

PLEASE NOTE:
Engineers who are already familiar with Xilinx 7-series or UltraScale devices devices with some Xilinx ISE Design Suite experience may prefer to attend the 4-day Vivado Adopter Class (which omits day one of this training, that's designed for new users). Please contact Doulos to discuss your specific requirements.

Engineers wishing to design with 6-series devices should contact Doulos for further information.

Prerequisites

  • Working HDL knowledge (VHDL, Verilog or SystemVerilog)
  • Digital design experience

Recommended additional training

  • Essential Tcl for Vivado teaches the essentials of the Tcl language with particular focus on its application within the Xilinx Vivado Design Suite*. It can be taken independently either before or after Vivado Adopter training as convenient (subject to availability).

Software Tools

  • Vivado HL Design or System Edition 2017.1

Hardware

  • Architecture: UltraScale and 7 series FPGAs*
  • Demo board (optional): Kintex® UltraScale FPGA KCU105 evaluation board or Kintex-7 FPGA KC705 board*

* This course focuses on the UltraScale and 7 series architectures. Check with Doulos for the specifics of the in-class lab environment or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Take advantage of the primary 7 series or UltraScale FPGA architecture resources
  • Identify synchronous design techniques
  • Describe how an FPGA is configured
  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize a systematic approach to apply timing constraints and achieve timing closure
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize a systematic approach to apply timing constraints and achieve timing closure
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

Course Outline

Day 1

  • Introduction to FPGA Architecture, 3D IC, SoC
    Overview of FPGA architecture, SSI technology, and SoC device architecture
  • CLB architecture
    Describes the resources available in CLBs, including LUTs and flip-flops
  • Clocking Resources
    Describes various clock resources, clocking layout, and routing in a design
  • I/O Logic Resources
    Overview of I/O resources and the IOB property for timing closure
  • Introduction to FPGA Configuration
    Describes how FPGAs can be configured
  • Configuration Process
    Understand the FPGA configuration process, such as device power up, CRC check, etc.
  • Configuration Modes
    Understand various configuration modes and select the suitable mode for a design
  • Synchronous Design Techniques
    Introduces synchronous design techniques used in an FPGA design
  • Register Duplication
    Use register duplication to reduce high fanout nets in a design
  • Pipelining
    Use pipelining to improve design performance

Day 2

  • Introduction to Vivado Design Flows
    Introduces the Vivado design flows: the project flow and non-project batch flow
  • Vivado Design Suite Project Mode
    Create a project, add files to the project, explore the Vivado IDE, and simulate the design
  • Synthesis and Implementation
    Create timing constraints according to the design scenario and synthesize and implement the design
  • Basic Design Analysis in the Vivado IDE
    Use the various design analysis features in the Vivado Design Suite
  • Vivado Design Suite I/O Pin Planning
    Use the I/O Pin Planning layout to perform pin assignments in a design
  • Vivado IP Flow
    Customize IP, instantiate IP, and verify the hierarchy of your design IP
  • Using an IP Container
    Use a core container file as a single file representation for an IP
  • Designing with IP Integrator
    Use the Vivado IP integrator to create the uart_led subsystem
  • Introduction to the Tcl Environment
    Introduces Tcl (tool command language)

Day 3

  • Managing Remote IP
    Store IP and related files remote to the current working project directory
  • Introduction to the Tcl Environment
    Introduces Tcl (tool command language)
  • Scripting in Vivado Design Suite Project Mode
    Explains how to write Tcl commands in the project-based flow for a design
  • Vivado Design Suite Non-Project Mode
    Create a design in the Vivado Design Suite non-project mode
  • Scripting in Vivado Design Suite Non-Project Mode
    Write Tcl commands in the non-project batch flow for a design
  • Design Analysis Using Tcl Commands
    Analyze a design using Tcl commands
  • Timing Constraints Wizard
    Use the Timing Constraints Wizard to apply missing timing constraints in a design
  • Timing Constraints Editor
    Introduces the timing constraints editor tool to create timing constraints
  • Introduction to Clock Constraints
    Apply clock constraints and perform timing analysis
  • Report Clock Networks
    Use report clock networks to view the primary and generated clocks in a design
  • Setup and Hold Timing Analysis
    Understand setup and hold timing analysis
  • Introduction to Vivado Reports
    Generate and use Vivado timing reports to analyze failed timing paths

Day 4

  • I/O Constraints and Virtual Clocks
    Apply I/O constraints and perform timing analysis
  • Timing Summary Report
    Use the post-implementation timing summary report to sign-off criteria for timing closure
  • Generated Clocks
    Use the report clock networks report to determine if there are any generated clocks in a design
  • Clock Group Constraints
    Apply clock group constraints for asynchronous clock domains
  • Introduction to Timing Exceptions
    Introduces timing exception constraints and applying them to fine tune design timing
  • Synchronization Circuits
    Use synchronization circuits for clock domain crossings
  • Report Clock Interaction
    Use the clock interaction report to identify interactions between clock domains
  • Timing Constraints Priority
    Identify the priority of timing constraints
  • Case Analysis
    Understand how to analyze timing when using multiplexed clocks in a design
  • Revision Control Systems in the Vivado Design Suite
    Use version control systems with Vivado design flows
  • UltraFast Design Methodology: Planning
    Introduces the methodology guidelines on planning and the UltraFast Design Methodology checklist
  • UltraFast Design Methodology: Design Creation and Analysis
    Overview of the methodology guidelines covered in this course

Day 5

  • HDL Coding Techniques
    Covers basic digital coding guidelines used in an FPGA design
  • Resets
    Investigates the impact of using asynchronous resets in a design
  • Baselining
    Use Xilinx-recommended baselining procedures to progressively meet timing closure
  • I/O Timing Scenarios
    Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data
  • System-Synchronous I/O Timing
    Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface
  • Source-Synchronous I/O Timing
    Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface
  • Report Datasheet
    Use the datasheet report to find the optimal setup and hold margin for an I/O interface
  • UltraFast Design Methodology: Design Closure
    Introduces the UltraFast design methodology guidelines on design closure
  • UltraFast Design Methodology: Advanced Techniques
    Introduces the methodology guidelines for advanced techniques
  • Introduction to Floorplanning
    Introduction to floorplanning and how to use Pblocks while floorplanning
  • Physical Optimization
    Use physical optimization techniques for timing closure

Optional Topics

The following topics are included in the course materials and, if time permits, may be covered during the course at the instructor’s discretion and according to the delegates’ interest.
  • Timing Simulation
    Simulate the design post-implementation to verify that a design works properly on hardware
  • Creating and Packaging Custom IP
    Create your own IP and package and include it in the Vivado IP catalog
  • Introduction to the Xilinx Tcl Store
    Introduces the Xilinx Tcl Store
  • Inference
    Infer Xilinx dedicated hardware resources by writing appropriate HDL code
  • Design Analysis and Floorplanning
    Explore the pre- and post-implementation design analysis features of the Vivado IDE
  • Vivado Design Suite ECO Flow
    Use ECO flow to make changes to a previously implemented design and apply changes to the original design
  • Bitstream Security
    Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication.

The current schedule for the Vivado Adopter Class for New Users is shown below:

Looking for Live Online Training? Click here

Course Dates:
May 22nd, 2018 Ringwood, UKCourse has started
June 5th, 2018 San Jose, CA Enquire
September 4th, 2018 Ankara, TR Enquire
September 25th, 2018 San Jose, CA Enquire
September 25th, 2018 Ringwood, UK Enquire
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