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Doulos Live Online Training

Xilinx - Vivado Design Suite ONLINE

(Also known as Vivado Design Suite for ISE Software Project Navigator Users* by Xilinx)
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IMPORTANT: This Live Online Instructor-Led course is for existing Xilinx® users who want to take full advantage of the Vivado® Design Suite feature set.

If you are new to Xilinx FPGA development it is essential that you attend the full 10-session, Vivado Adopter Class for New Users Online (which includes additional sessions on Xilinx FPGA essentials).

To view the full Vivado Adopter learning options, use the buttons on the right to get started.

Vivado Adopter Program

Summary course description:

This course provides an introduction to the Vivado Design Suite. Learn about:

  • Vivado Logo Vivado Design Suite projects
  • Design flow
  • Xilinx design constraints
  • Basic timing reports.


* This training by Doulos is based on materials provided by Xilinx from the course:
Vivado Design Suite for ISE Software Project Navigator Users

Training duration

3 sessions

Who Should Attend?

FPGA designers looking to utilize Vivado who:

  • currently use the Xilinx ISE® Design Suite
  • already have some familiarity with Xilinx 7-Series devices

PLEASE NOTE: Engineers who are unfamiliar with Xilinx devices with no prior Xilinx ISE Design Suite experience should attend Vivado Adopter Class for New Users. This course provides new users with a good grounding immediately prior to this more advanced training. Find out more using the link above or contact Doulos for further information.

Engineers wishing to design with 6-series devices should contact Doulos for further information.

Pre-requisites

  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge
  • Completion of sessions 1 & 2 of Vivado Adopter for New Users Online, or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture, and FPGA design techniques.

Recommended additional training

  • Essential Tcl for Vivado (online) teaches the essentials of the Tcl language with particular focus on its application within the Xilinx Vivado™ Design Suite*. It can be taken independently either before or after Vivado Adopter training as convenient (subject to availability).


Software Tools

  • Vivado System Edition 2017.3


Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Use the New Project Wizard to create a new Vivado IDE project
  • Describe the supported design flows of the Vivado IDE
  • Synthesize and implement the HDL design
  • Use the Vivado IDE I/O Planning layout to perform pin assignments
  • Use the Vivado IP integrator to create a block design
  • Create and package your own IP and add to the Vivado IP catalog to reuse
  • Create a Tcl script to create a project, add sources, and implement a design
  • Use Tcl scripting in non-project batch flows to synthesize, implement, and generate custom timing reports

Course Outline

  • Introduction to Vivado Design Flows
    Introduces the Vivado design flows: the project flow and non-project batch flow
  • Vivado Design Suite Project Mode
    Create a project, add files to the project, explore the Vivado IDE, and simulate the design
  • Synthesis and Implementation
    Create timing constraints according to the design scenario and synthesize and implement the design
  • Basic Design Analysis in the Vivado IDE
    Use the various design analysis features in the Vivado Design Suite
  • Vivado Design Suite I/O Pin Planning
    Use the I/O Pin Planning layout to perform pin assignments in a design
  • Vivado IP Flow
    Customize IP, instantiate IP, and verify the hierarchy of your design IP
  • Using an IP Container
    Use a core container file as a single file representation for an IP
  • Designing with IP Integrator
    Use the Vivado IP integrator to create the uart_led subsystem
  • Introduction to the Tcl Environment
    Introduces Tcl (tool command language)
  • Managing Remote IP
    Store IP and related files remote to the current working project directory
  • Introduction to the Tcl Environment
    Introduces Tcl (tool command language)
  • Scripting in Vivado Design Suite Project Mode
    Explains how to write Tcl commands in the project-based flow for a design
  • Vivado Design Suite Non-Project Mode
    Create a design in the Vivado Design Suite non-project mode
  • Scripting in Vivado Design Suite Non-Project Mode
    Write Tcl commands in the non-project batch flow for a design
  • Design Analysis Using Tcl Commands
    Analyze a design using Tcl commands
  • Timing Constraints Wizard
    Use the Timing Constraints Wizard to apply missing timing constraints in a design
  • Timing Constraints Editor
    Introduces the timing constraints editor tool to create timing constraints
  • Introduction to Clock Constraints
    Apply clock constraints and perform timing analysis
  • Report Clock Networks
    Use report clock networks to view the primary and generated clocks in a design
  • Setup and Hold Timing Analysis
    Understand setup and hold timing analysis
  • Introduction to Vivado Reports
    Generate and use Vivado timing reports to analyze failed timing paths

Course Dates:
August 12th, 2020 ONLINE Americas Enquire
August 19th, 2020 ONLINE EurAsia Enquire
October 7th, 2020 ONLINE Americas Enquire
October 14th, 2020 ONLINE EurAsia Enquire
December 2nd, 2020 ONLINE Americas Enquire
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