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Xilinx - Vivado FPGA Essentials

(This course is based on "Designing FPGAs Using the Vivado Design Suite" training developed by Xilinx)

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Course Description

This course will enable you to:

  • build an effective FPGA design using synchronous design techniques
  • understand the configuration process
  • instantiate appropriate device resources
  • use proper HDL coding techniques
  • make good pin assignments
  • set basic XDC constraints using the Timing Constraints Wizard
  • use the Vivado Design Suite to build, synthesize, implement, and download a design.

Training Duration

1 day

Who Should Attend?

  • Digital designers who have a working knowledge of an HDL (VHDL, Verilog or SystemVerilog) and who are new to Xilinx FPGAs.
  • Existing Xilinx ISE users who have little or no knowledge of 7-Series or UltraScale devices.


  • Working HDL knowledge (VHDL, Verilog or SystemVerilog)
  • Digital design experience

Software Tools

  • Vivado HL Design or System Edition 2017.1


  • Architecture: 7 series FPGAs
* This course focuses on the 7 series architecture. Please contact Doulos for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this training, you will know how to:

  • Take advantage of the primary 7 series FPGA architecture resources
  • Use the Project Manager to start a new project
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Make basic timing constraints using the Timing Constraints Wizard
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
  • Identify synchronous design techniques
  • Describe how an FPGA is configured.

Course Outline

Each topic is taught using either a lecture, a demo, or a lab, or a combination of these.  The labs comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.

  • Introduction to FPGA Architecture, 3D IC, SoC
    • Overview of FPGA architecture, SSI technology, and SoC device architecture.
  • HDL Coding Techniques
    • Covers basic digital coding guidelines used in an FPGA design.
  • Vivado Design Suite Project Mode
    • Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
  • Synthesis and Implementation
    • Create timing constraints according to the design scenario and synthesize and implement the design
  • Clocking Resources
    • Describes various clock resources, clocking layout, and routing in a design.
  • Timing Constraints Wizard
    • Use the Timing Constraints Wizard to apply missing timing constraints in a design.
  • I/O Logic Resources
    • Overview of I/O resources and the IOB property for timing closure.
  • Vivado Design Suite I/O Pin Planning
    • Use the I/O Pin Planning layout to perform pin assignments in a design.
  • Introduction to Vivado Reports
    • Generate and use Vivado timing reports to analyze failed timing paths. 
  • Introduction to FPGA Configuration
    • Describes how FPGAs can be configured.
  • Configuration Process
    • Understand the FPGA configuration process, such as device power up, CRC check, etc.
  • Synchronous Design Techniques
    • Introduces synchronous design techniques used in an FPGA design.
  • Register Duplication
    • Use register duplication to reduce high fanout nets in a design.
  • Pipelining
    • Use pipelining to improve design performance.


  • Timing Simulation
    • Simulate the design post-implementation to verify that a design works properly on hardware.
  • Configuration Modes
    • Understand various configuration modes and select the suitable mode for a design.
  • Xilinx Power Estimator Spreadsheet
    • Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.

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