Xilinx - Vivado FPGA Essentials(Also known as Essentials of FPGA Design by Xilinx)
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This course will enable you to:
- build an effective FPGA design using synchronous design techniques
- instantiate appropriate device resources
- use proper HDL coding techniques
- make good pin assignments
- set basic XDC constraints
- use the Vivado Design Suite to build, synthesize, implement, and download a design.
Who Should Attend?
- Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
- Existing Xilinx ISE users who have no previous experience or training with the Xilinx PlanAhead suite and little or no knowledge of Kintex-7 or Virtex-7 devices.
- Engineers wishing to design with 6-series devices should contact Doulos for further information.
- Engineers who are already familiar with Xilinx 7-series devices and have at least some familiarity with PlanAhead should instead attend Vivado Design Suite. See the recommended learning path above and please contact Doulos for further information.
- Working HDL knowledge (VHDL or Verilog)
- Digital design experience
- Vivado System Edition 2015.3
- Architecture: UltraScale™ and 7 series FPGAs*
- Demo board: Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*
* This course focuses on the 7 series architecture. Please contact Doulos for the specifics of the in-class lab board or other customizations.
After completing this training, you will know how to:
- Take advantage of the primary 7 series FPGA architecture resources
- Use the Project Manager to start a new project
- Identify the available Vivado IDE design flows (project based and non-project batch)
- Identify file sets (HDL, XDC, simulation)
- Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
- Synthesize and implement an HDL design
- Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
- Build custom IP with the IP Library utility
- Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)
- Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
- Describe and analyze common STA reports
- Identify synchronous design techniques
- Describe how an FPGA is configured.
- UltraFast Design Methodology Summary
- CLB Resources
- Introduction to the Vivado Design Suite
- Vivado Design Flows
- Lab 1: Vivado Tool Overview
- Demo: Visualization for Design Analysis
- Designing with IP
- Demo: IP Flow
- Demo:Designing with IPI
- Basic Timing Constraints and STA
- Demo: Reading Synthesis and Implementation Reports
- Lab 2: Vivado Synthesis, Implementation, and Timing Closure
- I/O Resources
- Other FPGA Resources
- Clocking Resources
- Lab 3: Designing with FPGA Resources
- Timing Reports
- Lab 4: Basic XDC and Timing Reports
- Synchronous Design Techniques
- FPGA Configuration
- UltraScale+ Families Overview
- Course Summary
- Appendix: Visualization for Analysis
- Appendix: Designing with IP
- Appendix: Designing with IP – IP Integrator Flow lab
- Lab 1: Vivado Tool Overview – Create a project in the Vivado Design Suite. Add files, simulate, and elaborate the design. Review the available reports, analyze the design with the Schematic and Hierarchy viewers, and run a design rule check (DRC). Finally, assign some of the I/O pins using the IO Planner.
- Lab 2: Vivado Synthesis, Implementation, and Timing Constraints – Synthesize and analyze the design with the Schematic viewer, apply a systematic approach to applying timing constraints and timing closure (i.e., understand the Xilinx baselining recommendation). Run basic static timing analysis using the check_timing and report_clock_utilization reports. Implement the design and analyze some timing-critical paths with the Schematic viewer. Download the bitstream to the demonstration board.
- Lab 3: Designing with FPGA Resources – Use the Xilinx Clocking Wizard to configure a clocking subsystem to provide various clock outputs and clock buffers to connect clock signals to global clock networks.
- Lab 4: Basic XDC and Timing Reports – Use timing constraints to improve design performance. Perform static timing analysis before and after implementation to validate the performance results.
- Appendix Lab: Designing with IP – IP Integrator Flow – Use the IP Vivado IP integrator to create a subsystem for a design. Generate the output products of the subsystem.
Looking for team-based training, or other locations?
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