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Zynq Logo Zynq System Architecture

Also known as Zynq SoC System Architecture by Xilinx

COVID-19 Update: This course is available Live Online worldwide

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Limited In-Person schedule available in Europe from September 2020

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Doulos In-Person Training

Course Description

The Xilinx® Zynq® SoC provides a new level of system design capabilities. This course provides experienced system architects with the knowledge to effectively architect a Zynq system on a chip.

This course presents the features and benefits of the Zynq architecture for making decisions on architecting a Zynq SoC project. It covers the architecture of the Arm® Cortex®-A9 processor-based processing system (PS) and the integration of programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq SoC.

The course also details the individual components that comprise the PS, I/O peripherals, timers, and caching, as well as the DMA, interrupt, and memory controllers. Emphasis will be placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.

Engineers who need a deeper understanding of the Arm® Cortex®-A9 processor should attend Arm Cortex-A9 for Zynq System Design, which describes the principles and internal details of the Cortex®-A9 processor architecture itself, as opposed to the architecture of the Zynq processing system (PS) of which it is a part.

Training Duration

2 days

Who Should Attend?

System architects who are interested in architecting a system on a chip using the Zynq SoC.


  • Digital system architecture design experience
  • Basic understanding of microprocessor architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience

Software Tools

  • Vivado® Design or System Edition 2017.1


  • Architecture: Zynq-7000 SoC*
  • Demo board: Zynq-7000 SoC ZC702 or Zed board*
* This course focuses on the Zynq-7000 SoC. Please contact Doulos for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the architecture and components that comprise the Zynq SoC processing system (PS)
  • Relate a user design goal to the function, benefit, and use of the Zynq SoC
  • Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
  • Analyze the tradeoffs and advantages of performing a function in software versus PL

Associated Courses

Course Outline

Day 1

  • Zynq SoC Architecture Overview
  • Inside the Application Processor Unit (APU)
  • Processor Input/Output Peripherals
  • Lab 1: Building a Zynq SoC Platform
  • Introduction to AXI
  • Zynq SoC PS/PL AXI Ports
  • Lab 2: Integrating Programmable Logic on the Zynq SoC

Day 2

  • Zynq SoC Configuration
  • Zynq SoC Memory Resources
  • Zynq SoC PL Design Architecture
  • Meeting Performance Goals
  • Lab 3: Using DMA on the Zynq SoC
  • Zynq SoC Software Design
  • Debugging the Zynq SoC
  • Lab 4: Debugging on the Zynq SoC
  • Zynq SoC Tools and Reference Designs
  • Lab 5: Running and Debugging a Linux Application on the Zynq SoC

Lab Descriptions

  • Lab 1: Building a Zynq SoC Platform - Examine the process of using the Vivado IP Integrator tool to create a simple processing system.
  • Lab 2: Integrating Programmable Logic on the Zynq SoC - Connect a programmable logic (PL) design to the embedded processing system (PS).
  • Lab 3: Using DMA on the Zynq SoC - Experiment with effectively using the PS DMA controller to move data between DDRx memory and a custom PL peripheral.
  • Lab 4: Debugging on the Zynq SoC - Evaluate debugging the hardware and software components of a Zynq design.
  • Lab 5: Running and Debugging a Linux Application on the Zynq SoC - Explore a software application executing under the Linux operating system on the Zynq SoC.

Course Dates:
December 2nd, 2020 Ringwood, UK Enquire
indicates CONFIRMED TO RUN courses.

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