Integrating the Arm Cortex-M3 in a Xilinx FPGA

Find a Training Course

Integrating the Arm Cortex-M3 in a Xilinx FPGA

1 hour session (All Time Zones)
Presenter: Dr David Cabanis

Doulos Principal Member Technical Staff

Asia and Europe

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)

Americas

Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)

Webinar Overview:

A best-of-both worlds solution for embedded systems

The combination of the widely acclaimed Arm® Cortex®-M MCU architecture with the performance of a Xilinx® FPGA provides more flexibility and greater scope for innovation in the creation of application-optimised designs.

Many Vivado® users are familiar with the Microblaze™ RISC processor. However, the Arm Cortex-M3 has a substantially different hardware architecture, with unique system integration aspects.

In this webinar we will examine the Cortex-M3 IP block and discuss its integration inside a Xilinx FPGA.

We will:

Examine the two main system busses, their use model and restrictions
Review the operations of the Nested Vectored Interrupt Controller (NVIC) and its interaction with a Wakeup Interrupt Controller (WIC)
Examine the memory management operations along with invasive and non-invasive debugging features of the core.

Dr David Cabanis Doulos Principal Member Technical Staff and Arm certified expert, will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.

Attendance is free of charge

If you have any queries, please contact webinars@doulos.com

More FREE online support resources with Doulos KnowHow

Doulos Knowhow includes

Technical information
Coding examples
Guidelines
Tips
Tutorials
Video guides
Downloads

Visit www.doulos.com/knowhow

Related training available from Doulos:

Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

Integrating the Arm Cortex-M3 in a Xilinx FPGA

Find a Training Course