SystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got Easier
Here you can download the following paper together with an archive that contains example SystemVerilog and SystemC source files:
- Event: DVCon 2010, San Jose, February 2010
- Title: "SystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got Easier"
- Author: John Aynsley, Doulos
- Abstract- The OVM and VMM methodologies each provide powerful, flexible and intuitive frameworks for the construction of SystemVerilog verification environments. However, many SystemVerilog users also have models written in C, C++, or sometimes SystemC. Furthermore, the emergence of the SystemC TLM-1 and TLM-2.0 transaction-level modeling standards is having an impact on communication styles within SystemVerlog verification environments. This paper offers practical guidance on using the SystemVerilog Direct Programming Interface (DPI) to integrate existing C, C++ and SystemC code into an OVM- or VMM-based SystemVerilog testbench without jeopardizing portability from one simulator to another. This is achieved by presenting a set of simple, robust guidelines for creating portable DPI code.
The premise of this paper is that you have a SystemVerilog test bench, probably constructed using the OVM or VMM verification methodology and hence written at the transaction level, communicating with a C/C++ or even a SystemC reference model through the DPI, that is, the SystemVerilog Direct Procedural Interface. Such a reference model would typically be untimed, but the paper also considers timed SystemC models.
The goal of the work described in the paper was very pragmatic: to get some DPI code that is portable and that actually works using the releases of SystemVerilog simulation tools from the big three EDA vendors that were current at the time. The desired outcome was to create a set of robust and easy-to-follow coding guidelines for the creation of portable DPI code. To find out how well we succeeded, you will have to read the paper!
One point needs to be clarified at the outset. Mixed language communication can occur at several possible abstraction levels. All the main EDA vendors have excellent support for mixed language simulation at the structural or RT-levels; for example, the instantiation of a SystemC module below a SystemVerilog test bench and communication between the two using wires or signals (the left column above). In theory, the DPI should allow simple function calls between SystemVerilog and SystemC (the middle column above), although the work done in this paper reveals some pitfalls in terms of portability between vendors which we know many users have already discovered for themselves. But it is at the transaction level (right column) that the problems really start, because no attempt has yet been made to standardize TL- communication across the language boundary. Individually, each EDA vendors provides a highly capable solution for mixed-language transaction-level modeling, but those solutions are all differentiated and non-portable. Addressing this issue of portability for transaction-level communication using the standard DPI is the subject of this paper.
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