Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions
Here you can download the following paper:
- Event: DVCon 2010, San Jose, February 2010
- Title: "Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions"
- Author: Doug Smith, Doulos
Most digital designs inherently possess some asynchronous behaviors. At a minimum, reset is usually asynchronous and many designs have multiple clock domains, introducing asynchronous communication between different parts of the design. Similarly, common interface protocols often have asynchronous signals and asynchronous requests and responses. Traditionally, writing checkers in Verilog for asynchronous behaviors is easy to do. Likewise, SystemVerilog provides immediate assertions that work in the same way since they are procedural and event based. Nevertheless, SystemVerilog introduces a rich set of concurrent assertion semantics (SVA) for writing checks that greatly simplify describing temporal functionality and validating a design's behavior.
While SVA offers some asynchronous control using disable iff, writing concurrent assertions that actually describe asynchronous behavior is not so straightforward. SVA properties require a clocking event, making them innately synchronous and cycle-based. When describing asynchronous behavior, the behavior of interest typically occurs after the asynchronous trigger appears. Unfortunately, SystemVerilog scheduling semantics make it rather difficult to describe asynchronous behavior because the assertion variable values must be sampled before the sampling trigger instead of afterwards. This leads assertion writers to use a sampling clock, which may not guarantee matching and optimal checking in all cases.
Alternatively, there are some simple approaches for describing asynchronous behavior using SVA that this paper will explore. The SystemVerilog scheduling semantics will be described as well as the difficulties it poses for describing the asynchronous behavior. Traditional approaches will be considered such as synchronizing to a clock, but better asynchronous alternatives are suggested and practical examples provided. Several practical issues using immediate assertions will also be discussed. In addition, some practical solutions are offered for other asynchronous scenarios such as asynchronous communication between clock domains or asynchronous control in real-world interface protocols like I2C.
Lastly, this paper will consider the various changes and additions to the SystemVerilog standard that are proposed for 2010, which may simplify describing asynchronous behavior. For example, new asynchronous controls like accept_on and reject_on have been introduced as well as new sampling semantics for constant and automatic variable arguments in procedural concurrent assertions and the new checker construct. A look at how deferred assertions might prove useful is also considered.
This paper should be of particular interest to anyone planning to use or currently using SystemVerilog assertions.
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