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Easier SystemVerilog with UVM: Taming the Beast


Here you can download the following paper:

  • Event: DVCon 2012, San Jose, February 2012
  • Title: "Easier SystemVerilog with UVM: Taming the Beast"
  • Author: John Aynsley, Doulos


Abstract

SystemVerilog has been widely adopted as a language for hardware design and verification. At the same time, SystemVerilog is a very large and complex language which can be daunting to learn and use, and differences still remain between implementations. SystemVerilog adoption has been given a new impetus in recent years with the introduction of UVM, the Universal Verification Methodology for SystemVerilog. The UVM codebase has provided a convergence point for SystemVerilog implementations and applications by creating a de facto SystemVerilog subset that all implementations must support. UVM uses a compact set of object-oriented programming features which are very general and expressive, and which are well-supported by the major implementations. When combined with other SystemVerilog features to express constraints, functional coverage, and to abstract the interface between the design-under-test and the class-based verification environment, the resultant set of language features is robust and sufficient for hardware verification.


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