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Making the most of SystemVerilog and UVM: Hints and Tips for new users


Here you can download the following paper and slides:

  • Event: SNUG Boston, September 2013
  • Title: "Making the most of SystemVerilog and UVM: Hints and Tips for new users"
  • Author: David Long, Doulos

  • Abstract- In the two years since UVM 1.0 was released by Accellera, Doulos has seen a big increase in the number of customers wanting to learn SystemVerilog: UVM has become the new standard verifi-cation environment for many companies. However, engineers often find that the size and com-plexity of the SystemVerilog language and the UVM class library make it hard to learn how to make effective use of their many features.

    This paper is intended to give guidance to engineers about some useful features of both SystemVerilog and UVM that are often overlooked, used in-correctly or simply avoided because they are perceived as being too hard to understand. The first part identifies the most common novice-user mistakes and sets out rules to avoid them. The second part discusses useful enhancements to verification capabilities that can be obtained from a deeper understanding of several SystemVerilog and UVM features. It provides simple examples and guidelines to show how each enhancement can be achieved.



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