Random Stability in SystemVerilog
Here you can download the following paper:
- Event: SNUG Austin, 2013
- Title: "Random Stability in SystemVerilog"
- Author: Doug Smith, Doulos
- Abstract- A common problem that arises with constrained random verification is reproducing random stimulus for verifying RTL bug fixes and locking down test stimulus for regressions. In SystemVerilog, this is referred to as random stability, which is both a function of thread locality and hierarchical seeding. This paper discusses random stability, especially the use of good random seeds and locking down random number generator (RNG) seeding for test reproducibility. In addition, the RNG seeding employed in the leading verification methodologies like VMM, OVM, and UVM will be examined, tested, and critiqued, highlighting the strengths and gotchas.
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