Easier UVM - for VHDL and Verilog UsersJohn Aynsley, Doulos, March 2011
Updated for UVM 1.0 and UVM 1.1
If you are already an experienced verification engineer familiar with SystemVerilog (or Vera or e or C++) you will probably have little trouble learning the UVM. This article, however, is aimed at a different audience; at those VHDL and Verilog engineers who feel they probably need to do a better job at functional verification, but have not yet found the time or the courage to take a deep dive into SystemVerilog.
In this article we take a look at UVM by considering how you would use UVM to represent ideas familiar to the Verilog or VHDL users, ideas such as design entities, modules, processes, ports, parameters, generics and configuration. Rather than trying trying to demonstrate all the fancy features of UVM, we will deliberately restrict ourselves to a small, well-behaved subset of the UVM library, which I will informally refer to as Easier UVM.
As a language, SystemVerilog provides the mechanisms you need to create verification components for checking, coverage collection, and stimulus generation, and to modify the behavior of those components as you write specific tests. But SystemVerilog provides more than this, so much more in fact that the learning curve can be daunting for non-specialists. If you are not a verification specialist, what you might need is just enough SystemVerilog to get you going so you can start to benefit from VIP re-use and as a base on which to build as your experience and confidence increase. The aim of Easier UVM is to introduce you to some coding guidelines for UVM that will enable you to do just that.
Easier UVM is not yet another verification methodology. It is UVM. The point is to somewhat restrict the range of features being used in order to make life easier for the novice. In short, where there are multiple ways of doing things we will pick just one, hopefully the cleanest and most well-behaved (though not necessarily your favorite if you happen to be a verification expert already).
If the subject of constrained random coverage-driven verification is unfamiliar to you, you might like to start by reading the UVM Verification Primer.
Open each of the topics below to see a UVM concept presented in terms familiar to the Verilog or VHDL users:
As regards Easier UVM this article is just a taster. We will publish more details over the coming months. Watch this space.
To get you started, we have put together an example written in the Easier UVM coding style that illustrates the points made above and demonstrates some of the new features added in UVM such as the end-of-test objection mechanism, callbacks, and the report catcher. We intend to build an expanded tutorial around this UVM example in due course, but in the meantime, enjoy!
UVM is here at last. This example runs unmodified using simulators from Cadence, Mentor, and Synopsys. Yippee!
Click here to download the source files for this example. In exchange, we will ask you to enter some personal details. To read about how we use your details, click here. On the registration form, you will be asked whether you want us to send you further information concerning other Doulos products and services in the subject area concerned.Previous: From OVM to UVM: Getting Started with UVM - A First Example
Easier UVM Coding Guidelines
Introduction to the Easier UVM Coding Guidelines
Summary of the Easier UVM Coding Guidelines
Detailed Explanation of the Easier UVM Coding Guidelines
Easier UVM Glossary
Easier UVM Coding Guidelines - Download
Easier UVM - Deeper Explanations
Coverage-Driven Verification Methodology
Requests, Responses, Layered Protocols and Layered Agents
How to Access a Parameterized SystemVerilog Interface from UVM
Easier UVM Code Generator
Easier UVM Code Generator - Download
Easier UVM Code Generator - Tutorial Part 1: Getting Started
Easier UVM Code Generator - Tutorial Part 2: Adding User-Defined Code
Easier UVM Code Generator - Tutorial Part 3: Adding the Register Layer
Easier UVM Code Generator - Tutorial Part 4: Hierarchical Verification Environments
Easier UVM Code Generator - Tutorial Part 5: Split Transactors
Easier UVM Code Generator - Frequently Asked Questions (FAQ)
Easier UVM Code Generator - Reference Guide
Easier UVM Video Tutorial
Introducing Easier UVM
Easier UVM - The Big Picture
Key Concepts of the Easier UVM Code Generator
Running Easier UVM in EDA Playground
Easier UVM - Components and Phases
Easier UVM - Configuration
TLM Connections in UVM
Easier UVM - Transaction Classes
Easier UVM - Sequences
Easier UVM - Tests
Easier UVM - Reporting
Easier UVM - Register Layer
Easier UVM - Parameterized Interfaces
Easier UVM - Scoreboards
The Finer Points of UVM Sequences (Recorded Webinar)
UVM Run-Time Phasing (Recorded Webinar)
A YouTube playlist with all the above videos and more
Easier UVM Paper and Poster
Easier UVM - Coding Guidelines and Code Generation - as presented at DVCon 2014
Easier UVM Q&A Forum
Easier UVM Google Group
Easier UVM Examples Ready-to-Run on EDA Playground
Minimal example with driver
Minimal example with coverage in a subscriber as well as driver and monitor.
Minimal example with register sequence and register block
Example with four interfaces/agents, two of which use a register model.
Minimal example with dual-top modules and split transactors
Minimal example showing a UVM sequence getting information from the config database
Minimal example showing features of objections and the command line processor
Minimal example showing the reporting features of UVM.
Example that drops an objection when coverage exceeds some threshold
Example that sends a response transaction from the driver back to the uvm_reg_adapter
Example that uses a frontdoor sequence to pass a response object back to the register sequence that called read/write
Example of a parameterized interface generated from an Easier UVM interface template file
Example that pulls in a user-defined parameterized interface
Example of a reference model with the Syosil scoreboard
Back to the full list of UVM Resources