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Easier UVM - for VHDL and Verilog Users

John Aynsley, Doulos, March 2011


From HDL Processes to the UVM Run Phase

UVM provides processes that execute during simulation, just like Verilog and VHDL. For example, here we see a VHDL design entity containing two concurrent processes:

-- VHDL
entity D is
end entity;

architecture V1 of D is
begin
  P1: process
  begin
    report "Hello world 1";
    wait;
  end process;
  
  P2: process
  begin
    report "Hello world 2";
    wait;
  end process;
end architecture;

And here is the UVM equivalent:

// UVM
class D extends uvm_component;

  `uvm_component_utils(D)
  
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  task run;
    fork
      begin: P1
        `uvm_info("", "Hello world 1", UVM_NONE)
      end
      begin: P2
        `uvm_info("", "Hello world 2", UVM_NONE)
      end
    join
  endtask

endclass

Any code written within the run method, which must be a SystemVerilog task, executes as a process during simulation. A UVM component can only have a single run method, so if you want multiple concurrent processes within a single UVM component, you have to spawn them off using fork-join. Note that there are no component instances within component D, so we don't need the build or connect methods.

Next:  From HDL Input and Output Ports to TLM Ports and Exports
Previous:  The Various Kinds of UVM Component

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