Easier UVM for Functional Verification by Mainstream Users
Here you can download the following paper:
- Event: DVCon 2011, San Jose, February 2011
- Title: "Easier UVM for Functional Verification
by Mainstream Users"
- Author: John Aynsley, Doulos
- SPECIAL VERSION UPDATED AND EXTENDED FOR UVM 1.0
This paper describes an approach to using Accellera's UVM, the Universal Verification Methodology, for functional verification by mainstream users as opposed to highly skilled verification specialists. It arises from experience at Doulos in teaching SystemVerilog and functional verification methodology to engineers from a broad cross-section of the hardware design and verification community. While much of the research and development in functional verification methodology is rightly focussed on the needs of power users as they solve the hardest verification problems, we find that the majority of mainstream users have a somewhat different focus, namely, how to become productive with SystemVerilog with a minimum of delay and specialist programming expertise. SystemVerilog and UVM provide mechanisms to create verification components for checking, coverage collection, and stimulus generation, and to modify the behavior of those components for specific tests. But SystemVerilog and UVM provide more than this, so much more in fact that the learning curve can be daunting for non-specialists.
We use simple examples to present a set of guidelines for the use of the UVM class library for functional verification. The goal is to enable engineers with experience in Verilog or VHDL to become productive in UVM by learning a small number of new coding idioms, selected to minimize the conceptual clutter they have to deal with. As users become fluent with this set of basic idioms, they can then branch out to embrace the full feature set of UVM as and when they need.
We describe coding guidelines to address the canonical structure of a UVM component and a UVM transaction, the construction of the UVM component hierarchy, the interface with the design-under-test, the use of UVM sequences, and the use of the factory and configuration mechanisms. Starting from these simple guidelines, engineers can create constrained random verification environments in an object-oriented coding style that are fully compliant with the UVM standard, and hence are interoperable with UVM verification IP from other sources.
This paper could also serve as an introductory tutorial on UVM for Verilog and VHDL users.
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Click here to download the source files for some Easier UVM examples related this paper. In exchange, we will ask you to enter some personal details. To read about how we use your details, click here. On the registration form, you will be asked whether you want us to send you further information concerning other Doulos products and services in the subject area concerned.