Monday 25 September 2017

Developing & Delivering KnowHow

Processes

In VHDL, the process statement contains sequential statements.

Processes are only permitted inside an architecture. The statements within processes execute sequentially, not concurrently.

Processes can be written in a variety of ways. The most common approach when using processes to describe designs is to use the form that has a sensitivity list.

Carrying on from the previous topic, we shall use two processes in our MUX_2 design, one to replace the AOI gate, the other to replace the inverter. We will then merge the two processes to see how a single process can be used to describe the design.

First of all, let's tackle the AOI gate. All we do is extract the signal assignment from the v1 architecture and insert it into the process. At this point, the signal assignment is a sequential signal assignment rather than a concurrent signal assignment. At this stage all we have done is wrap a process around the signal assignment.

v1_arch: process -- incomplete at this stage
begin
  F <= not ((A and B) or (C and D));
end process;

To make this process complete, we have to remember that we are describing a piece of combinational logic. From a conceptual point of view, the outputs of a combinational circuit CAN change when ANY one of the inputs changes. This means that we need to cause the process to execute when any of the ‘inputs' to the process changes. The way to do this is to create a sensitivity list for the process from the signals A, B, C and D. The sensitivity list follows the process keyword as shown:

v1_arch: process (A, B, C, D)
begin
  F <= not ((A and B) or (C and D));
end process;

However, inside the MUX_2 design, we are using the ports and signals of that design, so:

G2: process (SEL, A, SELB, B)
begin
  F <= not ((SEL and A) or (SELB and B));
end process;

Likewise for the inverter:

G1: process (SEL)
begin
  SELB <= not SEL;
end process;

We can combine these two processes into one:

combined: process (SEL, A, B)
begin
  F <= not ((SEL and A) or ((not SEL) and B));
end process;

Notice that not SEL from the G1 process was used to substitute the SELB in the G2 process. We now have a single process with a sensitivity list made up from only the MUX_2 ports - no internal signals.

In the next article in this series we will see how to take a more conceptual approach to coding processes, so that we can use more than just signal assignments to describe the behaviour of a design, in this case the MUX_2.

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