Monday 25 September 2017

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Test Benches : Part 1

So we have a design. But it's unproven. In this tutorial we look at designing a simple testbench in VHDL.

With VHDL, it is possible to model not only the hardware or system design, but also a test bench to apply stimulus to the design and to analyze the results, or compare the results of two simulations. In effect, VHDL can be used as a stimulus definition language as well as a hardware description language.

One consequence of using VHDL to model a test bench is that the test bench is portable between VHDL tools from different vendors.

Test Bench for MUX4

The entity declaration for a test bench (entity TEST_MUX4 is ... end;) is usually empty. This is because the test bench itself does not have any inputs or outputs. Test vectors are generated and applied to the unit under test within the test bench. Note that it is illegal to have an architecture body without an entity declaration.


A component declaration is needed (component MUX4 ... end component;) in order to pull the MUX4 entity into the test bench. Think of a component declaration as a chip socket. It allows a VHDL structural description to be written in a top-down manner, because the VHDL compiler can check the consistency of the design unit that uses the component before the corresponding design entity has been written.

In order that the VHDL simulator can bind (more VHDL jargon) the design entity MUX4 to the component MUX4, the names and types of the ports must match between the entity and the component.

Test Bench for MUX4

entity TEST_MUX4 is

library IEEE;
use IEEE.STD_LOGIC_1164.all;

architecture BENCH of TEST_MUX4 is

  component MUX4
  end component;

  -- signals


  -- signal assignments to create stimulus

  M: MUX4 port map (...);

end BENCH;

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