February 2004|Press release
Synopsys, Inc. (Nasdaq: SNPS), the world leader in semiconductor design software, and Doulos, Europe's leading independent methodology and language training company, today announced the availability of the first European SystemVerilog language training course, based on Synopsys' VCS® simulation platform. As an integral part of the training, attendees will gain hands-on experience with SystemVerilog's design and verification features using VCS.
"Effective use of SystemVerilog can deliver significant, additional benefits to designers," said Robert Hurley, business manager for Doulos. "SystemVerilog seeks to address the need for productivity improvements for both RTL and system-level design and verification. To enable engineers to exploit this potential, there is a clear need for solid language and methodology training delivered in the context of tools with strong SystemVerilog capability, such as VCS."
The jointly developed SystemVerilog Using VCS course covers application-focused topics, including SystemVerilog design extensions, SystemVerilog assertions and SystemVerilog interfaces which add a transaction-level modeling capability to the language. Design and verification engineers who attend the course will gain an advantage in implementing these features more quickly than those who don't have the advantage of focused training.
"SystemVerilog momentum is growing in our user community," said Ronald Niederhagen, Senior Director of Applications Services, Europe, at Synopsys, Inc. "As we roll out support for SystemVerilog across our implementation and verification platforms to include tools such as VCS and Design Compiler®, we are seeing an increasing demand for a dedicated language training."
The training course, "SystemVerilog Using VCS," will be available starting in March 2004. Pricing starts at 1,350 euros for a two-day class. The Doulos SystemVerilog Golden Reference Guide is included as part of the comprehensive set of course materials. Courses are scheduled over two consecutive days for Verilog users and three days for VHDL users and will be held at Synopsys' and Doulos' European training facilities. Classes are also offered for customer-designated site delivery.
SystemVerilog, the first hardware description and verification language (HDVL), is an extension to the IEEE 1364-2001 Verilog HDL and offers advanced design features to tackle the most complex next-generation designs, provides comprehensive testbench and assertions capabilities for integrated high-performance verification, and offers a designer-friendly direct programming interface for efficient interaction with C/C++ models, code and algorithms. For more information about SystemVerilog, visit http://www.systemverilog.org.
Synopsys, Inc. (Nasdaq: SNPS) is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.
Doulos is the leader for independent know-how in SoC, FPGA and ASIC design. As a fully independent company for over 13 years, its reputation for both development and delivery of the highest quality training solutions has extended across Europe and beyond. The company now boasts a customer base from 14 different countries including the leading semi-conductor and electronic systems design companies. Doulos offers generic independent training programs covering all aspects of design and verification methods for complex chip design. Doulos also partners with major EDA companies to provide tailored training solutions for mutual customers.
Marketing Communications Contacts:
Rachael Mundy +44 (0)1425 471223
David Marsden +44 (0)208 408 8000
Renae Veiga +1 650-584-1902
Synopsys, Design Compiler and VCS are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.