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February 2013|Press release
Doulos is pleased to announce a significant revision and updates to its established SystemVerilog portfolio at DVCon 2013 in San Jose.
Since its inception the spectrum of application and utility for SystemVerilog has developed significantly. In line with the demands for finely tuned training programs for application to both design and verification contexts, Doulos has led the market in providing 'fit for purpose' training programs that have rightly been referenced by customers in all parts of the industry.
In its 10th year of delivering SystemVerilog training, Doulos is announcing the results of a major revision which includes some new advanced materials on UVM and new in-depth course programs for SystemVerilog & UVM practitioners.
See the Doulos SystemVerilog training portfolio »
For further details please contact: firstname.lastname@example.org or your local Doulos office
DVCon is the premier conference for discussion of the functional design and verification of electronic systems.
DVCon is sponsored by Accellera Systems Initiative, an independent, not-for profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org.
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