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Common Mistakes in SystemVerilog

1 hour session (All Time Zones)
Presenter: Brian Jensen

Doulos Certified Training Instructor

Asia and Europe

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)

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Americas

Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)

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Webinar Overview:

This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.

Doulos CTI Brian Jensen, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using QuestaSim from Siemens-EDA  in the the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.

Topics include:

  • Wire vs Variable Assignments
  • Static vs Automatic Variables
  • Static vs Automatic Tasks
  • Assignments in Tasks – Pass-by-Copy
  • Assignments in Tasks – Pass-by-Reference
  • Enumerations
  • struct and packed struct
  • Equality Operators
  • Equality between vectors
  • SVA Temporal Behavior
Brian Jensen

Brian Jensen a Certified Training Instructor for Doulos, will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Attendance is free of charge

If you have any queries, please contact webinars@doulos.com

More FREE online support resources with Doulos KnowHow

Doulos Knowhow includes

  • Technical information
  • Coding examples
  • Guidelines
  • Tips
  • Tutorials
  • Video guides
  • Downloads

Visit www.doulos.com/knowhow

SystemVerilog training available from Doulos:

Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.