Verilog-AMS Adopter Class

Engineers who wish to extend their knowledge of Verilog to the modeling of analogue and mixed-signal electronic circuits.

Analogue and mixed-signal designers who wish to model their circuits at a more abstract level than is possible with SPICE.

Analogue engineers currently using proprietary Analogue HDLs who wish to migrate to a standard language.

Note: Any delegate who does not already know Verilog but who wishes to gain a good understanding of the Verilog language (for example because they need to model the digital elements of a complex mixed-signal system) is recommended to also attend the Comprehensive Verilog or Fast-Track Verilog for VHDL Users (ideally before attending this course).

For onsite courses, a selection of Verilog modules may be combined with the Verilog-AMS Adopter class to fully address the team requirements and background. Contact Doulos to discuss options that suit your needs

• The essential syntax of the Verilog-AMS language
• The semantics of Verilog-AMS with respect to circuit and mixed-signal simulation
• How to model basic electronic components
• How to model larger mixed-signal systems
• How to model at both circuit level and signal-flow level
• How to combine Verilog-AMS models with legacy models

Knowledge of SPICE or other analogue simulation tools would be advantageous, but is not essential. Some basic circuit theory will be used and a familiarity with the general concepts (such as Kirchhoff's laws) would be helpful.

Doulos training materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. Class fees include:

• Fully indexed class notes creating a complete reference manual
• Workbook full of practical examples to help you apply your knowledge This includes a tool tour guide (to support the Verilog-AMS simulation tool used in the practical sessions).

Introduction

Review of Verilog 1364-2005 • Verilog basics • Analogue modelling in Verilog • Other analogue HDLs

Verilog-AMS Basics

Definition of a discipline • Natures and tolerances • Nets, branches and references • Contribution statements • Net attributes • parameters • Examples: Resistor, capacitor

Circuit Modelling

Analog if and case statements • macromodels • signal flow ports • wreal • Frequency domain models • Filter functions • Examples: Diode, op amp, transmission line

Mixed-Signal Simulation

Analysis types • Initial conditions • Discontinuity • Time step control • Analogue events • Time dependencies • Limiting functions • Mixed-signal simulation cycle • Examples: Comparator, ADC, DAC

Advanced Modelling

'analog' functions • NMOS model • Optimising code • Noise modelling • Partial derivatives • Table modelling • Mixed disciplines • Paramset • Connect modules • Conclusions