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The Verilog-AMS Adopter Class is a comprehensive 2-day class covering the extension to Verilog for analogue and mixed-signal modelling, as well as the underpinning Verilog knowledge required. It includes Verilog-AMS language features, with examples of electronic circuits and systems, and new constructs are explained with reference to circuit simulation algorithms.
The course is split between interactive classroom-style lectures and practical hands-on exercises using a commercial simulation tool. The workshops are carefully designed to reinforce the material presented, and illustrate the scope of the language, with interesting exercises.
Engineers who wish to extend their knowledge of Verilog to the modeling of analogue and mixed-signal electronic circuits.
Analogue and mixed-signal designers who wish to model their circuits at a more abstract level than is possible with SPICE.
Analogue engineers currently using proprietary Analogue HDLs who wish to migrate to a standard language.
Note: Any delegate who does not already know Verilog but who wishes to gain a good understanding of the Verilog language (for example because they need to model the digital elements of a complex mixed-signal system) is recommended to also attend the Comprehensive Verilog or Fast-Track Verilog for VHDL Users (ideally before attending this course).
For onsite courses, a selection of Verilog modules may be combined with the Verilog-AMS Adopter class to fully address the team requirements and background. Contact Doulos to discuss options that suit your needs
Knowledge of SPICE or other analogue simulation tools would be advantageous, but is not essential. Some basic circuit theory will be used and a familiarity with the general concepts (such as Kirchhoff's laws) would be helpful.
Doulos training materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. Class fees include:
Review of Verilog 1364-2005 • Verilog basics • Analogue modelling in Verilog • Other analogue HDLs
Definition of a discipline • Natures and tolerances • Nets, branches and references • Contribution statements • Net attributes • parameters • Examples: Resistor, capacitor
Analog if and case statements • macromodels • signal flow ports • wreal • Frequency domain models • Filter functions • Examples: Diode, op amp, transmission line
Analysis types • Initial conditions • Discontinuity • Time step control • Analogue events • Time dependencies • Limiting functions • Mixed-signal simulation cycle • Examples: Comparator, ADC, DAC
'analog' functions • NMOS model • Optimising code • Noise modelling • Partial derivatives • Table modelling • Mixed disciplines • Paramset • Connect modules • Conclusions
Complete an enquiry form and a Doulos representative will get back to you.
Enquiry FormPrice on request