Designing an Integrated PCI Express System Online

• Hardware designers who want to create applications using AMD IP cores for PCI Express®
• Software engineers who want to understand the deeper workings of the AMD PCI Express solution
• System architects who want to leverage key AMD advantages related to performance, latency and bandwidth in PCI Express applications

• Vivado™ Design or System Edition

• Architecture: UltraScale™ and UltraScale+™ FPGAs*
• Demo board: Kintex™ UltraScale FPGA KCU105 board*

* This course focuses on the 7 series architecture. Please contact Doulos for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will know how to:

• Construct a basic PCIe system by:
• Selecting the appropriate core for your application
• Specifying requirements of an endpoint application
• Connecting this endpoint with the core
• Utilizing FPGA resources to support the core
• Simulating the design
• Identify the advanced capabilities of the PCIe specification protocol and feature set

Session 1

Session 2

Session 3

Session 4

Lab 1: Constructing the PCIe Core – This lab familiarizes you with the necessary flow for generating a AMD Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.

Lab 2: Simulating the PCIe Core – This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets.

Lab 3: Using the PCI Express Core in IP Integrator – This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.

Lab 4: Exploring the AMD DMA – This lab familiarizes you with all the necessary steps to set up and perform DMA transfers.

Lab 5: Implementing the PCIe Design – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode. 

Lab 6: Debugging the PCIe Design – This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation.