Xilinx FPGA Essentials & Vivado Design Suite Online

5 sessions

• Digital designers who have a working knowledge of an HDL (VHDL, Verilog or SystemVerilog) but are new to Xilinx FPGAs.
• Existing Xilinx ISE users who have little or no knowledge of 7-Series or UltraScale devices.

PLEASE NOTE:

Engineers who are already familiar with Xilinx 7-series or UltraScale devices devices with some Xilinx ISE Design Suite experience may prefer to attend the 3 session Vivado Design Suite (which omits the first two sessions of this training, designed for new users). Please contact Doulos to discuss your specific requirements.

Engineers wishing to design with 6-series devices should contact Doulos for further information.

• FPGA design experience
• Intermediate VHDL or Verilog knowledge
• Video Resources. The following videos contain essential content that will enable you to maximise the effectiveness of the Vivado training course:
  • http://www.xilinx.com/training/vivado/vivado-design-flows-overview.htm
  • http://www.xilinx.com/training/vivado/vivado-version-control-overview.htm

• Essential Tcl for Vivado (online) teaches the essentials of the Tcl language with particular focus on its application within the Xilinx Vivado™ Design Suite*. It can be taken independently either before or after Vivado Adopter training as convenient (subject to availability).
• It is strongly recommended that you take this training as part of the Doulos Vivado Adopter Class for New Users in which you will also learn about the underlying database and Static Timing Analysis (STA) mechanisms and utilize Tcl for navigating the design, creating Xilinx Design Constraints (XDC) and creating timing reports. You will also learn to make appropriate timing constraints for SDR, DDR, source-synchronous and system-synchronous interfaces for your FPGA design. You will also learn about the UltraFast™ Design Methodology, which encapsulates the FPGA design best practices and skills to be successful using the Vivado Design Suite.

Vivado System Edition 2017.3

After completing this comprehensive training, you will have the necessary skills to:

• Take advantage of the primary 7 series or UltraScale FPGA architecture resources
• Identify synchronous design techniques
• Describe how an FPGA is configured
• Use the New Project Wizard to create a new Vivado IDE project
• Describe the supported design flows of the Vivado IDE
• Synthesize and implement the HDL design
• Use the Vivado IDE I/O Planning layout to perform pin assignments
• Use the Vivado IP integrator to create a block design
• Create and package your own IP and add to the Vivado IP catalog to reuse
• Create a Tcl script to create a project, add sources, and implement a design
• Use Tcl scripting in non-project batch flows to synthesize, implement and generate custom timing reports

Sessions 1 - 2:  FPGA Essentials

• Introduction to FPGA Architecture, 3D IC, SoC
  Overview of FPGA architecture, SSI technology and SoC device architecture
• CLB architecture
  Describes the resources available in CLBs, including LUTs and flip-flops
• Clocking Resources
  Describes various clock resources, clocking layout, and routing in a design
• I/O Logic Resources
  Overview of I/O resources and the IOB property for timing closure
• Introduction to FPGA Configuration
  Describes how FPGAs can be configured
• Configuration Process
  Understand the FPGA configuration process, such as device power up, CRC check, etc.
• Configuration Modes
  Understand various configuration modes and select the suitable mode for a design
• Synchronous Design Techniques
  Introduces synchronous design techniques used in an FPGA design
• Register Duplication
  Use register duplication to reduce high fanout nets in a design
• Pipelining
  Use pipelining to improve design performance

Sessions 3 - 5:  Vivado Design Suite

• Introduction to Vivado Design Flows
  Introduces the Vivado design flows: the project flow and non-project batch flow
• Vivado Design Suite Project Mode
  Create a project, add files to the project, explore the Vivado IDE and simulate the design
• Synthesis and Implementation
  Create timing constraints according to the design scenario and synthesize and implement the design
• Basic Design Analysis in the Vivado IDE
  Use the various design analysis features in the Vivado Design Suite
• Vivado Design Suite I/O Pin Planning
  Use the I/O Pin Planning layout to perform pin assignments in a design
• Vivado IP Flow
  Customize IP, instantiate IP and verify the hierarchy of your design IP
• Using an IP Container
  Use a core container file as a single file representation for an IP
• Designing with IP Integrator
  Use the Vivado IP integrator to create the uart_led subsystem
• Introduction to the Tcl Environment
  Introduces Tcl (tool command language)
• Managing Remote IP
  Store IP and related files remote to the current working project directory
• Introduction to the Tcl Environment
  Introduces Tcl (tool command language)
• Scripting in Vivado Design Suite Project Mode
  Explains how to write Tcl commands in the project-based flow for a design
• Vivado Design Suite Non-Project Mode
  Create a design in the Vivado Design Suite non-project mode
• Scripting in Vivado Design Suite Non-Project Mode
  Write Tcl commands in the non-project batch flow for a design
• Design Analysis Using Tcl Commands
  Analyze a design using Tcl commands
• Timing Constraints Wizard
  Use the Timing Constraints Wizard to apply missing timing constraints in a design
• Timing Constraints Editor
  Introduces the timing constraints editor tool to create timing constraints
• Introduction to Clock Constraints
  Apply clock constraints and perform timing analysis
• Report Clock Networks
  Use report clock networks to view the primary and generated clocks in a design
• Setup and Hold Timing Analysis
  Understand setup and hold timing analysis
• Introduction to Vivado Reports
  Generate and use Vivado timing reports to analyze failed timing paths