Xilinx Vivado Design Suite

4 days

FPGA designers looking to utilize Vivado who:

• currently use the Xilinx ISE® Design Suite
• already have some familiarity with Xilinx 7-Series devices

PLEASE NOTE: Engineers who are unfamiliar with Xilinx devices with no prior Xilinx ISE Design Suite experience should attend Vivado Adopter Class for New Users. This course provides new users with a good grounding immediately prior to this more advanced training. Find out more using the link above or contact Doulos for further information.

• Basic knowledge of the VHDL or Verilog language
• Digital design knowledge
• Completion of day one of Vivado Adopter for New Users, or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture and FPGA design techniques.

• Essential Tcl for Vivado teaches the essentials of the Tcl language with particular focus on its application within the Xilinx Vivado Design Suite. It can be taken independently either before or after Vivado Adopter training as convenient (subject to availability).

• Vivado System Edition 2018.1

• Architecture: UltraScale and 7 series FPGAs*
• Demo board (optional): Kintex® UltraScale FPGA KCU105 evaluation board or Kintex-7 FPGA KC705 board*

* This course focuses on the UltraScale and 7 series architectures. Check with Doulos for the specifics of the in-class lab environment or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

• Use the New Project Wizard to create a new Vivado IDE project
• Describe the supported design flows of the Vivado IDE
• Synthesize and implement the HDL design
• Use the Vivado IDE I/O Planning layout to perform pin assignments
• Use the Vivado IP integrator to create a block design
• Create and package your own IP and add to the Vivado IP catalog to reuse
• Create a Tcl script to create a project, add sources and implement a design
• Use Tcl scripting in non-project batch flows to synthesize, implement and generate custom timing reports
• Apply clock and I/O timing constraints and perform timing analysis
• Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
• Describe and use the clock resources in a design
• Generate a DRC report to detect and fix design issues early in the flow
• Describe the "baselining" process to gain timing closure on a design
• Apply baseline constraints to determine if internal timing paths meet design timing objectives
• Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
• Analyze a timing report to identify how to center the clock in the data eye
• Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
• Define a properly constrained design
• Increase performance by utilizing FPGA design techniques
• Utilize floorplanning techniques to improve design performance
• Employ advanced implementation options, such as incremental compile flow and physical optimization techniques
• Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
• Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
• Build resets into your system for optimum reliability and design speed
• Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle

Day 1

• Introduction to Vivado Design Flows
  Introduces the Vivado design flows: the project flow and non-project batch flow
• Vivado Design Suite Project Mode
  Create a project, add files to the project, explore the Vivado IDE and simulate the design
• Synthesis and Implementation
  Create timing constraints according to the design scenario and synthesize and implement the design
• Basic Design Analysis in the Vivado IDE
  Use the various design analysis features in the Vivado Design Suite
• Vivado Design Suite I/O Pin Planning
  Use the I/O Pin Planning layout to perform pin assignments in a design
• Vivado IP Flow
  Customize IP, instantiate IP and verify the hierarchy of your design IP
• Using an IP Container
  Use a core container file as a single file representation for an IP
• Designing with IP Integrator
  Use the Vivado IP integrator to create the uart_led subsystem
• Introduction to the Tcl Environment
  Introduces Tcl (tool command language)

Day 2

• Managing Remote IP
  Store IP and related files remote to the current working project directory.
• Introduction to the Tcl Environment
  Introduces Tcl (tool command language).
• Scripting in Vivado Design Suite Project Mode
  Explains how to write Tcl commands in the project-based flow for a design
• Vivado Design Suite Non-Project Mode
  Create a design in the Vivado Design Suite non-project mode
• Scripting in Vivado Design Suite Non-Project Mode
  Write Tcl commands in the non-project batch flow for a design
• Design Analysis Using Tcl Commands
  Analyze a design using Tcl commands
• Timing Constraints Wizard
  Use the Timing Constraints Wizard to apply missing timing constraints in a design
• Timing Constraints Editor
  Introduces the timing constraints editor tool to create timing constraints
• Introduction to Clock Constraints
  Apply clock constraints and perform timing analysis
• Report Clock Networks
  Use report clock networks to view the primary and generated clocks in a design
• Setup and Hold Timing Analysis
  Understand setup and hold timing analysis
• Introduction to Vivado Reports
  Generate and use Vivado timing reports to analyze failed timing paths

Day 3

• I/O Constraints and Virtual Clocks
  Apply I/O constraints and perform timing analysis
• Timing Summary Report
  Use the post-implementation timing summary report to sign-off criteria for timing closure
• Generated Clocks
  Use the report clock networks report to determine if there are any generated clocks in a design
• Clock Group Constraints
  Apply clock group constraints for asynchronous clock domains
• Introduction to Timing Exceptions
  Introduces timing exception constraints and applying them to fine tune design timing
• Synchronization Circuits
  Use synchronization circuits for clock domain crossings
• Report Clock Interaction
  Use the clock interaction report to identify interactions between clock domains
• Timing Constraints Priority
  Identify the priority of timing constraints
• Case Analysis
  Understand how to analyze timing when using multiplexed clocks in a design
• Revision Control Systems in the Vivado Design Suite
  Use version control systems with Vivado design flows.
• UltraFast Design Methodology: Planning
  Introduces the methodology guidelines on planning and the UltraFast Design Methodology checklist
• UltraFast Design Methodology: Design Creation and Analysis
  Overview of the methodology guidelines covered in this course.

Day 4

• HDL Coding Techniques
  Covers basic digital coding guidelines used in an FPGA design
• Resets
  Investigates the impact of using asynchronous resets in a design
• Baselining
  Use Xilinx-recommended baselining procedures to progressively meet timing closure
• I/O Timing Scenarios
  Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture and edge/center aligned data
• System-Synchronous I/O Timing
  Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface
• Source-Synchronous I/O Timing
  Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface
• Report Datasheet
  Use the datasheet report to find the optimal setup and hold margin for an I/O interface
• UltraFast Design Methodology: Design Closure
  Introduces the UltraFast design methodology guidelines on design closure
• UltraFast Design Methodology: Advanced Techniques
  Introduces the methodology guidelines for advanced techniques
• Introduction to Floorplanning
  Introduction to floorplanning and how to use Pblocks while floorplanning
• Physical Optimization
  Use physical optimization techniques for timing closure

The following topics are included in the course materials and, if time permits, may be covered during the course at the instructor’s discretion and according to the delegates’ interest.

• Timing Simulation
  Simulate the design post-implementation to verify that a design works properly on hardware.
• Creating and Packaging Custom IP
  Create your own IP and package and include it in the Vivado IP catalog.
• Introduction to the Xilinx Tcl Store
  Introduces the Xilinx Tcl Store.
• Inference
  Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
• Design Analysis and Floorplanning
  Explore the pre- and post-implementation design analysis features of the Vivado IDE.
• Vivado Design Suite ECO Flow
  Use ECO flow to make changes to a previously implemented design and apply changes to the original design.
• Bitstream Security
  Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication.