The course introduces participants to the state-of-the-art techniques and methods in dynamic and formal design verification and how these fit into the modern verification process. Participants are equipped with foundation and advanced knowledge in design verification and have the opportunity to develop practical skills in dedicated lab exercises.
The course is flexible in terms of the design or verification language and EDA tools to be used in the practical lab exercises. It can be delivered as a 3 day course focused on methodologies for dynamic design verification followed by a 2 day course on formal verification, in particular model checking. The course can also be delivered in a bespoke sequence interleaving dynamic with formal design verification training modules and labs or shortened to 4 days depending on your preferences. Please contact Doulos to discuss your requirements.
Hands-on lab exercises are an integral part of the training. Lab exercises are designed to allow participants to practice the material presented and discussed in the training modules. Labs comprise approximately 33% of the class time.
Motivation • Cost of Bugs • Terminology • The Design Process • The Verification Process • Observability • Controllability • Verification Levels
Importance of Planning • Specifications • Feature Extraction • Identifying Corner Cases • Targets and Metrics • Unit and System-Level Verification Planning
Verification Tools and Languages • Basics of Testbenches • Driving and Checking • Limitations
Sign-off Criteria • Comprehensive Code Coverage • Functional Coverage • Combining Coverage Models • The Coverage Closure Challenge • Regressions • Verification Management
Motivation • Coverage with a focus on Functional Coverage • Testbench Automation • Modern Testbench Structure • Transactors • Coverage-driven Verification
How to predict expected results • Advanced Checkers • Reference Models • Self-checking Testbenches • Monitors • Scoreboards • Coherency
Terminology • Use • Temporal Properties • Property Formalization • Simulation with Assertions • Observability • Assertion Coverage • Property Re-use
Architecture of the top-level Testbench • Top-Level Testing • Controllability and Observability • Advanced Constrained Random Techniques • Configurations • Warm Loading • System-Level Properties and Assertions • System-Level Debug • Coverage above Unit Level • Power-Aware Verification • Accelleration • Validation • Performance Verification • Quality of Service
Specification • Plan • Verification Environment • Debug • Regression • Escape Analysis • Re-use • Advanced Verification Methodologies • Verification Review
Motivation • Terminology • Formal Property Checking • Developing Properties • Safety, Liveness and Invariant Properties • Environment and Assumptions • Interpreting the Outcome of Formal Property Checking • Coverage • Benefits and Strengths of Formal Verification
Bug Hunting • Bug Absence • Bug Analysis • Checking Bug Fixes • Coverage Closure • X-Propagation • Advanced Property Specification and Capture • Strategies for Coping with Complexity • Bounded Proof • Bug Avoidance • Finding Invariants • Property Re-use and libraries
Complete an enquiry form and a Doulos representative will get back to you.
Enquiry FormPrice on request