Expert Verilog Verification (2 days) is an intensive advanced application course. It teaches engineers how to increase productivity by enhancing their Verilog coding and application skills. The syllabus focuses on test benches and more recent techniques for verification such as scoreboarding and Transaction Level Verification (TLV). Also included is an overview of the SystemVerilog extensions to Verilog, with an assessment of their impact on both design and verification.
Carefully designed workshops comprise 50% of teaching time and enable engineers to apply their new skills in the context of the latest Verilog design tools, practices and methodologies.
Expert Verilog Verification forms the last 2 days of the 4-day Doulos Expert Verilog course.
Design engineers and verification engineers involved in Verilog test bench development or behavioural modelling for the purpose of functional verification
This is an advanced language and methodology training course. Prior attendance of the Doulos Comprehensive Verilog course (or equivalent) is required, and at least 6 months of ‘live’ project experience using Verilog is strongly recommended.
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
Verification flow • Black and white box testing styles • Code analysis to guide testing • Techniques for stimulus generation and output checking
Fine-grain concurrency with fork/join • The Verilog simulation cycle and its impact on coding style • Non-determinism and race hazards • Understanding the effect of delayed signal assignments
Structuring test fixtures with tasks and functions • Tactics for packaging code for maintainability and re-use • Advanced stimulus generators: Serial data, complex timing • Software encapsulation: Modules, local variables, multiple hierarchies
Bus functional models • Techniques for layering your test fixtures • Using Verilog modules like OO classes • Transaction generation using bus functional models • Re-use and flexibility of test fixture code
Specify blocks • Built-in timing checks • Strobing inputs and sampling outputs • Measuring delays • Storing inputs/outputs in a buffer • Collecting and filtering diagnostic data • Simple data visualisation techniques
Uses of component modelling • Component modelling methods • Choosing a component model • Structure of a component model • Handling asynchronous inputs • Storing inputs/outputs and sampling outputs • Measuring delays
Modelling memories • Imitating dynamic allocation in Verilog • Using public domain PLI applications to model large memories • Modelling external analogue subsystems • Signature analysis and other techniques for regression testing • Varying the timing of stimulus • Modelling communications channels • Random and directed-random tests
Incorporating PLI applications into your simulations • What the PLI can and can’t do • Two generations of the PLI – which to use? • Types of PLI application: Functions, stimulus generators, file access, component models • Pointers to functions in C • Function pointer tables • PLI application integration in various simulators
A tutorial review of recent changes in the Verilog language that are relevant to verification • Preview of SystemVerilog verification extensions
To meet varying specialist interests for team-based training, one or more of these optional modules can be integrated with the course by prior agreement with Doulos. These options are not available on scheduled public courses.
Verilog drive strengths • Modelling I/O primitives such as open-drain and pullup • Verilog switch primitives • Simulating the external analogue world using real numbers and sampled-time
Review of Verilog-1995 file I/O mechanisms • Verilog-2001 file I/O model and file reading functions • Reading structured data from text files • File-driven test fixtures
The PLI option requires a working knowledge of the C programming language.
PLI jargon • VPI and TF/ACC routines • Creating a simple PLI application • Linking PLI code to your Verilog simulation • Callback functions • Stimulus generators • Making PLI applications sensitive to input changes • Writing component models in the PLI
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