Expert Verilog is an intensive 4-day advanced application course. It teaches engineers how to increase productivity by enhancing their Verilog coding and application skills. Presented in two distinct modules, Expert Verilog focuses on language and synthesis issues, design re-use, test benches and the latest verification techniques – including PSL and an introduction to modern assertion-based approaches to verification. Each module also includes an overview of the 2001, 2005 and SystemVerilog extensions to Verilog, with an assessment of their impact on both design and verification.
The modules, which may be attended together or independently, follow on from the industry standard Doulos course, Comprehensive Verilog. Carefully designed workshops comprise 50% of teaching time and enable engineers to apply their new skills in the context of the latest Verilog design tools, practices and methodologies.
Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:
The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.
This is an advanced language and methodology training course. Prior attendance of the Doulos Comprehensive Verilog course (or equivalent) is required, and at least 6 months of 'live' project experience using Verilog is strongly recommended. Delegates attending the Expert Design module must have knowledge and experience of register transfer level coding and synthesis, using Verilog.
Doulos Course materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course materials include:
The RTL subset - writing synthesis-friendly code • Incomplete assignment, latches and re-circulation • Asynchronous inputs to clocked processes • Inference versus instantiation • The limits of combinational, register and arithmetic optimisation • Timing constraints, area constraints, and optimisation options • Multiple clocks and partitioning clock domains • Synthesis methodology for large designs
Coding styles for efficient and maintainable designs • Using local variables • Blocking and non-blocking assignments - recommendations, pitfalls and myths
Implementing sequential algorithms in RTL • Coding styles and design tradeoffs for Finite State Machines
Language level re-use • Standard component re-use • Impact of IP on design process • Writing re-usable Verilog • RTL Verilog style for capturing IP • Isolating tool and technology dependencies • Readability and maintainability • Comments and meaningful names • Language facilities for re-use, including Verilog-2001 improvements
Why use assertions in your designs? • Introduction to Properties • Property Specification Language (PSL) and SystemVerilog Assertions (SVA) • Introduction to temporal operators • Embedding assertions in your designs
A tutorial review of recent changes in the Verilog language that are relevant to design • Preview of SystemVerilog design enhancements
Verification flow • Black and white box testing styles • Code analysis to guide testing • Techniques for stimulus generation and output checking
Fine-grain concurrency with fork/join • The Verilog simulation cycle and its impact on coding style • Non-determinism and race hazards • Understanding the effect of delayed signal assignments
Structuring test fixtures with tasks and functions • Tactics for packaging code for maintainability and re-use • Advanced stimulus generators: Serial data, complex timing • Software encapsulation: Modules, local variables, multiple hierarchies
Bus functional models • Techniques for layering your test fixtures • Using Verilog modules like OO classes • Transaction generation using bus functional models • Re-use and flexibility of test fixture code
Specify blocks • Built-in timing checks • Strobing inputs and sampling outputs • Measuring delays • Storing inputs/outputs in a buffer • Collecting and filtering diagnostic data • Simple data visualisation techniques
Uses of component modelling • Component modelling methods • Choosing a component model • Structure of a component model • Handling asynchronous inputs • Storing inputs/outputs and sampling outputs • Measuring delays
Modelling memories • Imitating dynamic allocation in Verilog • Using public domain PLI applications to model large memories • Modelling external analogue subsystems • Signature analysis and other techniques for regression testing • Varying the timing of stimulus • Modelling communcations channels • Random and directed-random tests
(Note: No prior experience of C is assumed)
Incorporating PLI applications into your simulations • What the PLI can and can’t do • Two generations of the PLI – which to use? • Types of PLI application: Functions, stimulus generators, file access, component models • Pointers to functions in C • Function pointer tables • PLI application integration in various simulators
A tutorial review of recent changes in the Verilog language that are relevant to verification • Preview of SystemVerilog verification extensions
To meet varying specialist interests for team-based training, one or more of these optional modules can be integrated with the course by prior agreement with Doulos. These options are not available on scheduled public courses.
Verilog drive strengths • Modelling I/O primitives such as open-drain and pullup • Verilog switch primitives • Simulating the external analogue world using real numbers and sampled-time
Review of Verilog-1995 file I/O mechanisms • Verilog-2001 file I/O model and file reading functions • Reading structured data from text files • File-driven test fixtures
The PLI option requires a working knowledge of the C programming language.
PLI jargon • VPI and TF/ACC routines • Creating a simple PLI application • Linking PLI code to your Verilog simulation • Callback functions • Stimulus generators • Making PLI applications sensitive to input changes • Writing component models in the PLI
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