PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content as a scheduled in-person class and delivers comparable learning outcomes. Daily sessions comprise 4-6 hours of class contact time.
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VHDL for Designers ONLINE prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC designers.
Uniquely, delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.
The content of this course is identical to that of the face-to-face course VHDL for Designers (previously VHDL for FPGA Design). It uses the same agenda, presentation content, exercises/labs and supporting course materials (in electronic format).
No previous knowledge of VHDL or a software language is required. Delegates must have attended Essential Digital Design Techniques or an equivalent course, or have a good working knowledge of digital hardware design.
Delegates preparing to design complex FPGAs or ASICs with VHDL may benefit from attending the following advanced training options from Doulos, specifically Advanced VHDL and Expert VHDL. This ONLINE course is a suitable pre-requisite for either of these classes.
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include (in electronic format):
Because of enabling remote access on short order, demo boards cannot be shipped to customer addresses but it may be possible for delegates to use boards they already have access to locally. However remote access is provided to appropriate simulation and synthesis tools supporting the FPGA design flow.
Note: the learning outcomes are not primarily dependent on delegates having access to suitable demo boards
The scope and application of VHDL • Design and tool flow • FPGAs • The VHDL world
The basic VHDL language constructs • VHDL source files and libraries • The compilation procedure • Synchronous design and timing constraints
Simulation • Synthesis • Place-and-Route • Device programming
Entities and Architectures • Std_logic • Signals and Ports • Concurrent assignments • Instantiation and Port Maps • The Context Clause
The Process statement • Sensitivity list versus Wait • Signal assignments and delta delays • Register transfers • Default assignment • Simple Testbenches
If statements • Conditional signal assignments and Equivalent process • Transparent latches • Case statements • Synthesis of combinational logic
VHDL types • Standard packages • Integer subtypes • Std_logic and std_logic_vector • Slices and concatenation • Integer and vector values
Arithmetic operator overloading • Arithmetic packages • Mixing integers and vectors • Resizing vectors • Resource sharing
RISING_EDGE • Asynchronous set or reset • Synchronous inputs and clock enables • Synthesisable process templates • Implying registers
Enumeration types • VHDL coding styles for FSMs • State encoding • Unreachable states and input hazards
Array types • Modelling memories • IP Generators • Instantiating generated components • Implementing ROMs
TEXTIO • READ and WRITE • Using TEXTIO for testbench stimulus and outputs • STD_LOGIC_TEXTIO
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