Advanced Level - 2 days
Advanced FPGA Design tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools.
This course requires the Essentials & Design for Performance course as a prerequisite. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the Spartan®-6 and Virtex®-6 FPGAs.
This course is also available for in-house delivery. Please contact a member of the sales team to discuss your requirements.
Engineers who seek advanced FPGA design training using Xilinx tools to improve FPGA performance and utilization while also increasing productivity
- Xilinx ISE Design Suite: Logic or System Edition: Version 14.1
- Architecture: 7 series FPGAs*
- Demo board: Kintex™-7 KC705 board*
*Please contact Doulos for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will know how to:
- Create and edit a User Constraint File (UCF)
- Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfaces
- Implement designs via the Tcl command line
- Use the PlanAhead™ tool to create area constraints
- Use design preservation techniques to simplify design ripple effects
- Change signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor
- Lab 1: Timing Closure Review
- UCF Editing
- Lab 2: UCF Editing
- Advanced I/O Timing
- Lab 3: Advanced I/O Timing
- Tcl Scripting
- Lab 4: Tcl Scripting
- Floorplanning and Effective Layout
- Lab 5: Floorplanning
- Design Preservation Techniques
- Lab 6: Leveraging Design Preservation for Predictable Results
- FPGA Editor: Viewing and Editing a Routed Design
- Lab 7: Advanced FPGA Editor
Note: Labs will be based on Xilinx ISE 13 or 14 software (see above).
- Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.
- Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.
- Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.
- Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.
- Lab 5: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.
- Lab 6: Leveraging Design Preservation for Predictable Results – Utilize partitions to preserve timing results from one iteration to the next.
- Lab 7: FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope™ Pro tool cores.