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Comprehensive PlanAhead Design Techniques

Course Description

Learn to use the PlanAhead™ software tool to achieve repeatable increases in performance by managing your FPGA I/O and implementation.
Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, completing synthesis and implementation with the PlanAhead tool, synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.

Course Duration

3 days

Who Should Attend?

FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.

Software Tools
  • Xilinx ISE Design Suite: Logic or System Edition 14.1
  • Architecture: 7 series FPGAs*
  • Demo board: None*
* This course focuses on the 7 series FPGA architecture. Please contact Doulos for the specifics of the in-class lab board or other customizations.
What will you learn?
After completing this comprehensive training, you will have the necessary skills to:
  • Use the PlanAhead software features and benefits
  • Import designs into the PlanAhead software project environment
  • Assign I/O pins for optimum speed
  • Run the Design Rule Checker (DRC) and perform noise analysis
  • Import HDL sources and elaborate and analyze RTL netlists
  • Implement the design with different implementation strategies
  • Instantiate a core from the Xilinx IP Catalog
  • Take advantage of the ISim simulator
  • Use the PlanAhead software integrated with the ISE Project Navigator software environment
  • Apply the hierarchical viewer and timing report information to make the best area constraints
  • Group the best logic into Pblocks
  • Import HDL sources, elaborate, and analyze an RTL netlist
  • Implement the design with different implementation strategies
  • Analyze design statistics, connectivity, timing, placement, and timing critical paths
  • Insert ChipScope Pro tool debug cores
  • Floorplan the design to improve performance and preserve successful implementation results
  • Make placement constraints for dedicated hardware resources
Course Outline

Day 1

  • PlanAhead Software Benefits and Features Overview
  • PlanAhead Software Project Manager
  • Lab 1: Getting Started with the PlanAhead Software
  • I/O Pin Planning
  • Lab 2: Assigning I/O Pins
  • CORE Generator Software Integration
  • Lab 3: Core Integration
  • Static Timing Analysis with the PlanAhead Software
  • Project Navigator Integration
  • Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course

Day 2

  • PlanAhead Software Review
  • Lab 4: PlanAhead Software Review
  • RTL Development and Analysis
  • Lab 5: RTL Analysis
  • Placing Dedicated Resources
  • Lab 6: Placing Dedicated Resources
  • Introduction to Pblocks
  • Floorplanning Techniques

Day 3

  • Floorplanning Case Studies
  • Lab 7: Design Analysis and Floorplanning for Performance
  • Design Preservation with Partitions
  • Lab 8: Leveraging Design Preservation for Predictable Results
  • Debugging with the ChipScope Pro Tool
  • Lab 9: Debugging with the ChipScope Tool
  • Tcl Scripting in the PlanAhead Software
  • Lab 10: Tcl Ccommands
  • (Optional): Team Design
  • (Optional): Routing Optimization in Virtex-6 Devices
Lab Descriptions
Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.
  • Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead software so that you can synthesize, implement, perform timing analysis, view logical and device resources, and generate a bitstream. Also introduces the PlanAhead software's environment and views.
  • Lab 2: Assigning I/O Pins – Introduces the PlanAhead software ’s pin planning environment for performing I/O pin assignment. You will create a pin planning project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, examine clock logic placement, and make pin assignments.
  • Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator software with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.
  • Lab 4: PlanAhead Software Review – Illustrates the steps you take to import source HDL files into the PlanAhead tool and synthesize, implement, and analyze the results. Also introduces the PlanAhead tool environment and views.
  • Lab 5: RTL Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).
  • Lab 6: Placing Dedicated Resources – Introduces the methods for assigning location constraints to dedicated hardware resources. Demonstrates how to assign dedicated clocking resources, work with multi-function I/O pins, and complete a SSN noise analysis.
  • Lab 7: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.
  • Lab 8: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.
  • Lab 9: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.
  • Lab 10: Tcl Commands – Use the Tcl interface in the PlanAhead software.

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