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Designing with the Virtex-6 Family

Course Description

Are you interested in learning how to effectively utilize Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family.


Topics covered include device overviews, CLB construction, MMCM clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP and source-synchronous resources. Soft memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology and GTP transceivers) are also introduced.


This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
Course Duration
2 days
  • Essentials of FPGA Design course
  • Intermediate VHDL or Verilog knowledge
Software Tool
  • Xilinx ISE® Design Suite: Logic or System Edition 13.1
  • Architecture: Virtex-6 FPGA*
  • Demo board: Spartan-6 FPGA SP605 board

* This course focuses on the Spartan-6 and Virtex-6 architectures. Please contact Doulos for the specifics of the in-class lab board or other customizations.

What will you learn?
After completing this comprehensive training, you will have the necessary skills to:
  • Describe all the functionality of the 6-input LUT and the CLB construction of the Virtex-6 FPGA
  • Specify the CLB resources and the available slice configurations for the Virtex-6 FPGA
  • Define the block RAM, FIFO and DSP resources available for the Virtex-6 FPGA
  • Properly design for the I/O block and SERDES resources
  • Identify the MMCM and clock routing resources included with this family
  • Identify the supported soft memory controllers for the Virtex-6 FPGA
  • Properly code your HDL to get the most out of the Virtex-6 FPGA
  • Describe the additional dedicated hardware for all the Virtex-6 family members
Course Outline

Day 1

  • Virtex-6 FPGA Overview
  • CLB Architecture
  • HDL Coding Techniques
  • Lab 1: CLB Resources
  • Memory Resources
  • Lab 2: DSP Resources
  • Basic I/O Resources


Day 2

  • Virtex-6 FPGA I/O Resources
  • Lab 3: I/O Resources
  • Basic Clocking Resources
  • Virtex-6 FPGA Clocking Resources
  • Lab 4: Clocking Resources
  • Memory Controllers
  • Dedicated Hardware
Lab Descriptions
  • Lab 1: CLB Resources –Using XST, synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.
  • Lab 2: DSP Resources – Using XST, synthesize and implement a 24x17 MAC. Device usage will be verified via the FPGA Editor. Using the CORE Generator™ tool, construct, instantiate and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.
  • Lab 3: I/O Resources – Using the ISE tools, complete the construction of the transmit SERDES datapath. Explore, through simulation, the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the Virtex-6 FPGA tile used for construction of a high-speed interface.
  • Lab 4: Clocking Resources – Using the Clocking Wizard, build and optimize the appropriate MMCM and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.

Looking for team-based training, or other locations?

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