COVID-19 Update: View Doulos COVID News Updates »
This course is available Live Online worldwide: View the Live Online full course description »
Limited In-Person schedule available in Europe from September 2020: View dates and locations »
In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.
Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.
FPGA designers and logic designers
- Verilog or VHDL experience (or Comprehensive Verilog or Comprehensive VHDL course)
- Familiarity with logic design (state machines and synchronous design)
- Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
- Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
- Vivado® System Edition 2016.3
- Mentor Graphics Questa Advanced Simulator 10.4
- Architecture: 7 series and UltraScale FPGAs*
- Demo board: Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*
* This course focuses on the UltraScale and 7 series architectures. Please contact Doulos
for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will know how to:
- Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
- Effectively utilize the following features of the gigabit transceivers:
- 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
- Pre-emphasis and receive equalization
- Use the Transceivers Wizards to instantiate GT primitives in a design
- Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
- Use the IBERT design to verify transceiver links on real hardware
- 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview
- 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets
- Transceiver IP Generation - Transceiver Wizard
- Lab 1: Transceiver Core Generation
Use the Transceivers Wizard to create instantiation templates.
- Transceiver Simulation
- Lab 2: Transceiver Simulation
Simulate the transceiver IP by using the IP example design.
- PCS Layer General Functionality
- PCS Layer Encoding
- Lab 3: 64B/66B Encoding
Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design and analyze the results.
- Transceiver Implementation
- Lab 4: Transceiver Implementation
Implement the transceiver IP by using the IP example design.
- PMA Layer Details
- PMA Layer Optimization
- Lab 5: IBERT Design
Verify transceiver links on real hardware.
- Transceiver Test and Debugging
- Lab 6: Transceiver Debugging
Debug transceiver links.
- Transceiver Board Design Considerations
- Transceiver Application Examples