Learn to manage design performance, plan an I/O pin layout and implement by using the PlanAhead™ software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores and completing synthesis and implementation with the PlanAhead tool.
Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.
FPGA designers, system architects and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.
- Xilinx ISE Design Suite: Logic or System Edition 14.1
- Architecture: 7 series FPGAs*
- Demo board: None*
* This course focuses on the 7 series FPGA architecture. Please contact Doulos
for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will have the necessary skills to:
- Use the PlanAhead software features and benefits
- Import designs into the PlanAhead software project environment
- Assign I/O pins for optimum speed
- Run the Design Rule Checker (DRC) and perform noise analysis
- Import HDL sources and elaborate and analyze RTL netlists
- Implement the design with different implementation strategies
- Instantiate a core from the Xilinx IP Catalog
- Take advantage of the ISim simulator
- Use the PlanAhead software integrated with the ISE Project Navigator software environment
- PlanAhead Software Benefits and Features Overview
- PlanAhead Software Project Manager
- Lab 1: Getting Started with the PlanAhead Software
- I/O Pin Planning
- Lab 2: Assigning I/O Pins
- CORE Generator Software Integration
- Lab 3: Core Integration
- Static Timing Analysis with the PlanAhead Software
- Project Navigator Integration
- Introduction to the Advanced Design with the PlanAhead Analysis and Design Tool Course
Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead software.
- Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead software so that you can synthesize, implement, perform timing analysis, view logical and device resources and generate a bitstream. Also introduces the PlanAhead software's environment and views.
- Lab 2: Assigning I/O Pins – Introduces the PlanAhead software's pin planning environment for performing I/O pin assignment. You will create a pin planning project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, examine clock logic placement and make pin assignments.
- Lab 3: Core Integration – Illustrates the integration of the CORE Generator software with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog and view the generated core with the Schematic viewer.